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Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters AD9776A/AD9778A/AD9779A
FEATURES
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 to 50 Novel 2x, 4x, and 8x interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP
GENERAL DESCRIPTION
The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit, high dynamic range digital-to-analog converters (DACs) that provide a sample rate of 1 GSPS, permitting a multicarrier generation up to the Nyquist frequency. They include features optimized for direct conversion transmission applications, including complex digital modulation and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the ADL537x FMOD series from Analog Devices, Inc. A 3-wire interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 10 mA to 30 mA. The devices are manufactured on an advanced 0.18 m CMOS process and operate on 1.8 V and 3.3 V supplies for a total power consumption of 1.0 W. They are enclosed in a 100-lead thin quad flat package (TQFP).
APPLICATIONS
Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMax, GSM, LTE Digital high or low IF synthesis Internal digital upconversion capability Transmit diversity Wideband communications: LMDS/MMDS, point-to-point
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. CMOS data input interface with adjustable setup and hold. Novel 2x, 4x, and 8x interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth.
QUADRATURE MODULATOR/ MIXER/ AMPLIFIER
2. 3. 4. 5.
TYPICAL SIGNAL CHAIN
COMPLEX I AND Q DC DC DIGITAL INTERPOLATION FILTERS I DAC FPGA/ASIC/DSP Q DAC POST DAC ANALOG FILTER A
06452-114
LO
AD9776A/AD9778A/AD9779A
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9776A/AD9778A/AD9779A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 6 Digital Input Data Timing Specifications ................................. 7 AC Specifications.......................................................................... 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 16 Terminology .................................................................................... 24 Theory of Operation ...................................................................... 25 Differences Between AD9776/AD9778/ AD9779 and AD9776A/AD9778A/AD9779A............................................... 25 3-Wire Interface .............................................................................. 26 General Operation of the Serial Interface ............................... 26 Instruction Byte .......................................................................... 26 Serial Interface Port Pin Descriptions ..................................... 27 MSB/LSB Transfers..................................................................... 27 3-Wire Interface Register Map ...................................................... 28 Interpolation Filter Architecture .................................................. 33 Interpolation Filter Bandwidth Limits .................................... 37 Inverse Sinc Filter ....................................................................... 38 Sourcing the DAC Sample Clock ................................................. 39 Direct Clocking .......................................................................... 39 Clock Multiplication .................................................................. 39 Driving the REFCLK Input ....................................................... 42 Full-Scale Current Generation ..................................................... 43 Internal Reference ...................................................................... 43 Gain and Offset Correction .......................................................... 44 I/Q Channel Gain Matching ..................................................... 44 Auxiliary DAC Operation ......................................................... 44 LO Feedthrough Compensation .............................................. 45 Results of Gain and Offset Correction .................................... 45 Input Data Ports ............................................................................. 46 Single Port Mode ........................................................................ 46 Dual Port Mode .......................................................................... 46 Input Data Referenced to DATACLK ...................................... 46 Input Data Referenced to REFCLK ......................................... 47 Optimizing the Data Input Timing.......................................... 48 Device Synchronization ................................................................. 49 Synchronization Logic Overview ............................................. 49 Synchronizing Devices to a System Clock .............................. 50 Interrupt Request Operation .................................................... 50 Power Dissipation ........................................................................... 51 Power-Down and Sleep Modes................................................. 52 Evaluation Board Overview .......................................................... 53 Evaluation Board Operation ..................................................... 53 Outline Dimensions ....................................................................... 55 Ordering Guide .......................................................................... 55
Rev. B | Page 2 of 56
AD9776A/AD9778A/AD9779A
REVISION HISTORY
9/08--Rev. A to Rev. B Changed Serial Peripheral Interface (SPI) to 3-Wire Interface Throughout ................................................................................... 1 Change to Features Section .............................................................. 1 Change to Applications Section ...................................................... 1 Changes to Integral Nonlinearity (INL) Parameter, Table 1 ....... 5 Changes to DAC Clock Input (REFCLK+, REFCLK-) Parameter, Table 2 ........................................................................ 6 Changes to Input Data Parameter, Table 3..................................... 7 Changes to Hold Time Parameters, Table 3................................... 7 Added 3-Wire Interface Parameter, Table 3................................... 7 Added Reset Parameter, Table 3 ...................................................... 7 Changes to Endnotes, Table 3 .......................................................... 7 Added Exposed Pad Notation to Figure 3, Changes to Table 7 ...... 10 Added Exposed Pad Notation to Figure 4, Changes to Table 8 ...... 12 Added Exposed Pad Notation to Figure 5, Changes to Table 9 ...... 14 Changes to DATACLK Delay Range Section ..............................25 Changes to Version Register Section ............................................25 Changes to Table 10 ........................................................................25 Changes to Table 12 ........................................................................26 Changes to Table 13 ........................................................................28 Changes to Table 14 ........................................................................29 Changes to Interpolation Filter Architecture Section ................33 Changes to Figure 60 ......................................................................34 Changes to Table 19 ........................................................................36 Changes to Interpolation Filter Bandwidth Limits Section.......37 Changes to Figure 70 ......................................................................37 Added Digital Modulation Section ...............................................37 Added Table 20 and Table 21; Renumbered Sequentially ..........38 Added Inverse Sinc Filter Section .................................................38 Added Figure 71; Renumbered Sequentially ...............................38 Changes to Clock Multiplication Section ....................................39 Changes to Figure 72 ......................................................................39 Changes to Configuring the PLL Band Select Value Section ....39 Changes to Configuring the PLL Band Select with Temperature Sensing Section ...........................................................................41 Changes to Known Temperature Calibration with Memory Section .........................................................................................41 Changes to Set-and-Forget Device Option Section ....................41 Added Table 26 ................................................................................41 Changes to Internal Reference Section.........................................43 Changed Transmit Path Gain and Offset Correction Heading to Gain and Offset Correction ......................................................44 Changes to I/Q Channel Gain Matching Section .......................44 Changes to Auxiliary DAC Operation Section ........................... 44 Replaced Figure 79 .......................................................................... 45 Deleted Figure 79; Renumbered Sequentially ............................. 41 Changes to LO Feedthrough Compensation Section................. 45 Changes to Table 28 ........................................................................ 47 Changes to Optimizing the Data Input Timing Section ............ 48 Change to Synchronization Logic Overview Section ................. 49 Changes to Figure 88 ...................................................................... 49 Changes to Figure 101 .................................................................... 53 Deleted Using the ADL5372 Quadrature Modulator Section and Figure 104 .................................................................................... 51 Deleted Evaluation Board Schematics Section and Figure 105; Renumbered Sequentially ......................................................... 52 Deleted Figure 106 .......................................................................... 53 Deleted Figure 107 .......................................................................... 54 Deleted Figure 108 .......................................................................... 55 Deleted Figure 109 .......................................................................... 56 Deleted Figure 110 .......................................................................... 57 Deleted Figure 111 .......................................................................... 58 Deleted Figure 112 .......................................................................... 59 Updated Outline Dimensions........................................................ 60 3/08--Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Added Note 2 ..................................................................................... 4 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 6 Changes to Thermal Resistance Section ........................................ 7 Inserted Table 6 ................................................................................. 8 Changes to Pin 39 Description, Table 7 ......................................... 9 Changes to Pin 39 Description, Table 8 ....................................... 10 Changes to Pin 39 Description, Table 9 ....................................... 12 Changes to Theory of Operation Section .................................... 23 Changes to Table 10 ........................................................................ 23 Changes to Table 13 ........................................................................ 26 Changes to Table 14 ........................................................................ 27 Changes to Interpolation Filter Architecture Section ................ 33 Replaced Sourcing the DAC Sample Clock Section ................... 36 Replaced Transmit Path Gain and Offset Correction Section ........ 40 Replaced Input Data Ports Section ............................................... 42 Replaced Device Synchronization Section .................................. 45 Deleted Figure 112 to Figure 117 .................................................. 58 8/07--Revision 0: Initial Version
Rev. B | Page 3 of 56
AD9776A/AD9778A/AD9779A
FUNCTIONAL BLOCK DIAGRAM
SYNC_O SYNC_I DATACLK DELAY LINE DATA ASSEMBLER DELAY LINE CLOCK GENERATION/DISTRIBUTION CLOCK MULTIPLIER 2x/4x/8x REFCLK+ REFCLK-
SINC^-1
n x fDAC /8 n = 0, 1, 2 ... 7 Q LATCH 2x 2x 2x
COMPLEX MODULATOR
P1D[15:0]
I LATCH
16-BIT I DAC
OUT1_P OUT1_N
2x
2x
2x
P2D[15:0]
SINC^-1
16-BIT Q DAC
OUT2_P OUT2_N
REFERENCE AND BIAS
VREF I120
DIGITAL CONTROLLER 10 10 SERIAL PERIPHERAL INTERFACE POWER-ON RESET 10 GAIN GAIN GAIN GAIN
AUX1_P AUX1_N AUX2_P AUX2_N
06452-001
AD9779A
10
SDO SDIO SCLK CSB
Figure 2. AD9779A Functional Block Diagram
Rev. B | Page 4 of 56
AD9776A/AD9778A/AD9779A SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Gain DAC Monotonicity MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage AUXILIARY DAC OUTPUTS Resolution Full-Scale Output Current1 Output Compliance Range (Source) Output Compliance Range (Sink) Output Resistance Auxiliary DAC Monotonicity REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD33 DVDD18 POWER CONSUMPTION 2 1x Mode, fDAC = 100 MSPS, IF = 1 MHz 2x Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL Off 2x Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL On 4x Mode, fDAC/4 Modulation, fDAC = 500 MSPS, IF = 137.5 MHz, Q DAC Off 8x Mode, fDAC/4 Modulation, fDAC = 1 GSPS, IF = 262.5 MHz Power-Down Mode Power Supply Rejection Ratio, AVDD33 OPERATING RANGE
1 2
Min
AD9776A Typ Max 12 0.1 0.86
Min
AD9778A Typ Max 14 0.65 1.5
Min
AD9779A Typ Max 16 2.1 6.0
Unit Bits LSB LSB
-0.001 8.66 -1.0
0 2 20.2
+0.001 31.66 +1.0
-0.001 8.66 -1.0
0 2 20.2 10 Guaranteed 0.04 100 30 10
+0.001 31.66 +1.0
-0.001 8.66 -1.0
0 2 20.2
+0.001 31.66 +1.0
10 Guaranteed 0.04 100 30 10 -1.998 0 0.8 +1.998 1.6 1.6 1 Guaranteed 1.2 5 3.13 1.70 3.13 1.70 3.3 1.8 3.3 1.8 250 498 588 572 980 2.5 -0.3 -40 +25 9.8 +0.3 +85 3.47 2.05 3.47 2.05 300 3.13 1.70 3.13 1.70 -1.998 0 0.8
10 Guaranteed 0.04 100 30 10 +1.998 1.6 1.6 -1.998 0 0.8 +1.998 1.6 1.6
% FSR % FSR mA V M
ppm/C ppm/C ppm/C Bits mA V V M
1 Guaranteed 1.2 5 3.3 1.8 3.3 1.8 250 498 588 572 980 2.5 -0.3 -40 +25 9.8 +0.3 +85 3.47 2.05 3.47 2.05 300 3.13 1.70 3.13 1.70
1 Guaranteed 1.2 5 3.3 1.8 3.3 1.8 250 498 588 572 980 2.5 -0.3 -40 +25 9.8 +0.3 +85 3.47 2.05 3.47 2.05 300
V k V V V V mW mW mW mW mW mW % FSR/V C
Based on a 10 k external resistor. See the Power Dissipation section for more details.
Rev. B | Page 5 of 56
AD9776A/AD9778A/AD9779A
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2.
Parameter CMOS INPUT LOGIC LEVEL Input VIN Logic High Input VIN Logic Low Maximum Input Data Rate at Interpolation 1x 2x 4x 8x Conditions Min 2.0 0.8 300 250 200 112.5 125 137.5 2.4 At 250 MHz, into 5 pF load SYNC_I+ = VIA, SYNC_I- = VIB 40 825 -100 20 80 Additional limits on fSYNC_I apply; see description of Register 0x05, Bits[3:1], in Table 14 0.4 0.55 SYNC_O+ = VOA, SYNC_O- = VOB, 100 termination 1375 1025 150 1150 80 400 300 900 1000 1100 250 200 100 800 400 250 1250 120 2000 500 mV mV mV mV mV mV MHz MHz MHz MHz 120 250 50 0.4 60 1575 +100 Typ Max Unit V V MSPS MSPS MSPS MSPS MSPS MSPS V V % mV mV mV MSPS ns ns
DVDD18, CVDD18 = 1.8 V 5% DVDD18, CVDD18 = 1.9 V 5% DVDD18, CVDD18 = 2.0 V 2%
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37) 1 Output VOUT Logic High Output VOUT Logic Low DATACLK Output Duty Cycle LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I-) Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH - VIDTHL Receiver Differential Input Impedance, RIN LVDS Input Rate Setup Time, SYNC_I to REFCLK Hold Time, SYNC_I to REFCLK LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O-) Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage, |VOD| Output Offset Voltage, VOS Output Impedance, RO DAC CLOCK INPUT (REFCLK+, REFCLK-) Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate
Single-ended
DVDD18, CVDD18 = 1.8 V 5%, PLL off DVDD18, CVDD18 = 1.9 V 5%, PLL off DVDD18, CVDD18 = 2.0 V 2%, PLL off DVDD18, CVDD18 = 2.0 V 2%, PLL on
1
Specification is at a DATACLK frequency of 100 MHz into a 1 k load, with maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests using an external buffer for this signal.
Rev. B | Page 6 of 56
AD9776A/AD9778A/AD9779A
DIGITAL INPUT DATA TIMING SPECIFICATIONS
All modes, -40C to +85C. Table 3.
Parameter INPUT DATA 1 Setup Time Hold Time Setup Time Hold Time LATENCY 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation Inverse Sync 3-WIRE INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High, tPWH Minimum Pulse Width Low, tPWL Setup Time, tDS Hold Time, tDH Setup Time, tDS Data Valid, tDV POWER-UP TIME 2 RESET Minimum Pulse Width, High
1
Conditions Input data to DATACLK Input data to DATACLK Input data to REFCLK Input data to REFCLK With or without modulation With or without modulation With or without modulation With or without modulation
Min 3.0 -0.05 -0.80 3.80
Typ
Max
Unit ns ns ns ns
25 70 146 297 18 40 12.5 12.5
DACCLK cycles DACCLK cycles DACCLK cycles DACCLK cycles DACCLK cycles MHz ns ns ns ns ns ns ms DACCLK cycles
SDIO to SCLK SDIO to SCLK CSB to SCLK SDO to SCLK
2.8 0.0 2.8 2.0 260 2
Specified values are with PLL disabled. Timing vs. temperature and data valid keep out windows (that is, the minimum amount of time valid data must be presented to the device to ensure proper sampling) are delineated in Table 28. 2 Measured from CSB rising edge when Register 0x00, Bit 4, is written from 1 to 0 with the VREF decoupling capacitor equal to 0.1 F.
Rev. B | Page 7 of 56
AD9776A/AD9778A/AD9779A
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. Table 4.
Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 60 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 100 MHz NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING fDAC = 200 MSPS, fOUT = 80 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 80 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 100 MHz fDAC = 491.52 MSPS, fOUT = 200 MHz W-CDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 100 MHz fDAC = 491.52 MSPS, fOUT = 200 MHz Min AD9776A Typ Max 82 81 80 85 87 80 75 75 Min AD9778A Typ Max 82 81 80 85 87 85 81 80 Min AD9779A Typ Max 82 82 80 87 91 85 81 81 Unit dBc dBc dBc dBc dBc dBc dBc dBc
-152 -155 -157.5
-155 -159 -160
-158 -160 -161
dBm/Hz dBm/Hz dBm/Hz
76 69
78 73
79 74
dBc dBc
77.5 76
80 78
81 78
dBc dBc
Rev. B | Page 8 of 56
AD9776A/AD9778A/AD9779A ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter AVDD33, DVDD33 DVDD18, CVDD18 AGND DGND CGND I120, VREF, IPTAT OUT1_P, OUT1_N, OUT2_P, OUT2_N, AUX1_P, AUX1_N, AUX2_P, AUX2_N P1D[15:0], P2D[15:0] DATACLK, TXENABLE REFCLK+, REFCLK- RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O-, SYNC_I+, SYNC_I-, CSB, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range With Respect To AGND, DGND, CGND AGND, DGND, CGND DGND, CGND AGND, CGND AGND, DGND AGND AGND Rating -0.3 V to +3.6 V -0.3 V to +2.1 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to AVDD33 + 0.3 V -1.0 V to AVDD33 + 0.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
For optimal thermal performance, the exposed paddle (EPAD) should be soldered to the ground plane for the 100-lead, thermally enhanced TQFP package. Typical JA and JC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing JA. Table 6. Thermal Resistance
Package Type 100-Lead TQFP EPAD Soldered EPAD Not Soldered JA 19.1 27.4 JB 12.4 JC 7.1 Unit C/W C/W
DGND DGND CGND DGND
-0.3 V to DVDD33 + 0.3 V -0.3 V to DVDD33 + 0.3 V -0.3 V to CVDD18 + 0.3 V -0.3 V to DVDD33 + 0.3 V
+125C -65C to +150C
ESD CAUTION
Rev. B | Page 9 of 56
AD9776A/AD9778A/AD9779A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OUT2_N OUT1_N AVDD33 AVDD33 AVDD33 AVDD33 AVDD33
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK- CGND CGND CVDD18
AVDD33
AUX1_N
AUX2_N
OUT2_P
OUT1_P
AUX1_P
AUX2_P
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
1 2 3 4 5 6 7 8 9 PIN 1
75 74
I120 VREF IPTAT AGND IRQ RESET CSB SCLK SDIO SDO PLL_LOCK DGND SYNC_O+ SYNC_O- DVDD33 DVDD18 NC NC NC NC P2D0 DGND DVDD18 P2D1 P2D2
ANALOG DOMAIN
73 72 71
DIGITAL DOMAIN
70 69 68
AD9776A
TOP VIEW (Not to Scale)
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CVDD18 10 CGND 11 AGND 12 SYNC_I+ 13 SYNC_I- 14 DGND 15 DVDD18 16 P1D11 17 P1D10 18 P1D9 19 P1D8 20 P1D7 21 DGND 22 DVDD18 23 P1D6 24 P1D5 25
TXENABLE/IQSELECT
NC
NC
NC
DGND
NC
DATACLK
DGND
P1D4
P1D3
P1D2
P1D1
P1D0
P2D9
P2D8
P2D7
P2D6
P2D5
P2D4
P2D11
DVDD18
DVDD33
P2D10
NOTES 1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE.
DVDD18
P2D3
NC = NO CONNECT
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 3. AD9776A Pin Configuration
Table 7. AD9776A Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK- CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I- DGND DVDD18 Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Clock Ground. Differential Clock Input. Differential Clock Input. Clock Ground. Clock Ground. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Analog Ground. Differential Synchronization Input. Differential Synchronization Input. Digital Ground. 1.8 V Digital Supply. Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Rev. B | Page 10 of 56
Mnemonic P1D11 P1D10 P1D9 P1D8 P1D7 DGND DVDD18 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 NC DGND
Description Port 1, Data Input D11 (MSB). Port 1, Data Input D10. Port 1, Data Input D9. Port 1, Data Input D8. Port 1, Data Input D7. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Port 1, Data Input D2. Port 1, Data Input D1. Port 1, Data Input D0 (LSB). No Connect. Digital Ground.
06452-002
AD9776A/AD9778A/AD9779A
Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Mnemonic DVDD18 NC NC NC
DATACLK
DVDD33 TXENABLE/ IQSELECT P2D11 P2D10 P2D9 DVDD18 DGND P2D8 P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 DVDD18 DGND P2D0 NC NC NC NC DVDD18 DVDD33 SYNC_O- SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK
Description 1.8 V Digital Supply. No Connect. No Connect. No Connect. Data Clock Output. 3.3 V Digital Supply. Transmit Enable. In single port mode, this pin also functions as IQSELECT. Port 2, Data Input D11 (MSB). Port 2, Data Input D10. Port 2, Data Input D9. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. Port 2, Data Input D4. Port 2, Data Input D3. Port 2, Data Input D2. Port 2, Data Input D1. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D0 (LSB). No Connect. No Connect. No Connect. No Connect. 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output. Digital Ground. PLL Lock Indicator. 3-Wire Interface Port Data Output. 3-Wire Interface Port Data Input/Output. 3-Wire Interface Port Clock.
Pin No. 69 70 71 72 73
Mnemonic CSB RESET IRQ AGND IPTAT
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33
Description 3-Wire Interface Port Chip Select Bar. Reset, Active High. Interrupt Request. Analog Ground. Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 A at 25C with approximately 20 nA/C slope. This pin should remain floating. Voltage Reference Output. 120 A Reference Current. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. Analog Ground. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Ground. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Ground. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply.
Rev. B | Page 11 of 56
AD9776A/AD9778A/AD9779A
OUT2_N OUT1_N AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AUX1_N AUX2_N OUT2_P OUT1_P AUX1_P AUX2_P AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK- CGND CGND CVDD18
1 2 3 4 5 6 7 8 9 PIN 1
75 74
I120 VREF IPTAT AGND IRQ RESET CSB SCLK SDIO SDO PLL_LOCK DGND SYNC_O+ SYNC_O- DVDD33 DVDD18 NC NC P2D0 P2D1 P2D2 DGND DVDD18 P2D3 P2D4
ANALOG DOMAIN
73 72 71
DIGITAL DOMAIN
70 69 68
AD9778A
TOP VIEW (Not to Scale)
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CVDD18 10 CGND 11 AGND 12 SYNC_I+ 13 SYNC_I- 14 DGND 15 DVDD18 16 P1D13 17 P1D12 18 P1D11 19 P1D10 20 P1D9 21 DGND 22 DVDD18 23 P1D8 24 P1D7 25
TXENABLE/IQSELECT
NC
DGND
NC
DATACLK
DGND
P1D6
P1D5
P1D4
P1D3
P1D2
P1D1
P1D0
P2D9
P2D8
P2D7
P2D6
P2D13
P2D12
P2D11
DVDD18
DVDD33
NOTES 1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE.
DVDD18
P2D10
P2D5
NC = NO CONNECT
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 4. AD9778A Pin Configuration
Table 8. AD9778A Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Mnemonic CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK- CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I- DGND DVDD18 P1D13 P1D12 Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Clock Common. Differential Clock Input. Differential Clock Input. Clock Ground. Clock Ground. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Analog Ground. Differential Synchronization Input. Differential Synchronization Input. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D13 (MSB). Port 1, Data Input D12. Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Rev. B | Page 12 of 56
Mnemonic P1D11 P1D10 P1D9 DGND DVDD18 P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 DGND DVDD18 P1D0 NC NC
Description Port 1, Data Input D11. Port 1, Data Input D10. Port 1, Data Input D9. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D8. Port 1, Data Input D7. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Port 1, Data Input D2. Port 1, Data Input D1. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D0 (LSB). No Connect. No Connect.
06452-003
AD9776A/AD9778A/AD9779A
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Mnemonic
DATACLK
DVDD33 TXENABLE/ IQSELECT P2D13 P2D12 P2D11 DVDD18 DGND P2D10 P2D9 P2D8 P2D7 P2D6 P2D5 P2D4 P2D3 DVDD18 DGND P2D2 P2D1 P2D0 NC NC DVDD18 DVDD33 SYNC_O- SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET
Description Data Clock Output. 3.3 V Digital Supply. Transmit Enable. In single port mode, this pin also functions as IQSELECT. Port 2, Data Input D13 (MSB). Port 2, Data Input D12. Port 2, Data Input D11. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D10. Port 2, Data Input D9. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. Port 2, Data Input D4. Port 2, Data Input D3. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D2. Port 2, Data Input D1. Port 2, Data Input D0 (LSB). No Connect. No Connect. 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output. Digital Ground. PLL Lock Indicator. 3-Wire Interface Port Data Output. 3-Wire Interface Port Data Input/Output. 3-Wire Interface Port Clock. 3-Wire Interface Port Chip Select Bar. Reset, Active High.
Pin No. 71 72 73
Mnemonic IRQ AGND IPTAT
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33
Description Interrupt Request. Analog Ground. Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 A at 25C with approximately 20 nA/C slope. This pin should remain floating. Voltage Reference Output. 120 A Reference Current. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. Analog Ground. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Ground. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Ground. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply.
Rev. B | Page 13 of 56
AD9776A/AD9778A/AD9779A
OUT2_N OUT1_N AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AUX1_N AUX2_N OUT2_P OUT1_P AUX1_P AUX2_P AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK- CGND CGND CVDD18
1 2 3 4 5 6 7 8 9 PIN 1
75 74
I120 VREF IPTAT AGND IRQ RESET CSB SCLK SDIO SDO PLL_LOCK DGND SYNC_O+ SYNC_O- DVDD33 DVDD18 P2D0 P2D1 P2D2 P2D3 P2D4 DGND DVDD18 P2D5 P2D6
ANALOG DOMAIN
73 72 71
DIGITAL DOMAIN
70 69 68
AD9779A
TOP VIEW (Not to Scale)
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CVDD18 10 CGND 11 AGND 12 SYNC_I+ 13 SYNC_I- 14 DGND 15 DVDD18 16 P1D15 17 P1D14 18 P1D13 19 P1D12 20 P1D11 21 DGND 22 DVDD18 23 P1D10 24 P1D9 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TXENABLE/IQSELECT
DGND
DATACLK
DGND
P1D8
P1D7
P1D6
P1D5
P1D4
P1D3
P1D2
P1D1
P1D0
P2D9
P2D8
P2D15
P2D14
P2D13
P2D12
P2D11
DVDD18
DVDD33
NOTES 1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE.
DVDD18
P2D10
P2D7
Figure 5. AD9779A Pin Configuration
Table 9. AD9779A Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Mnemonic CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK- CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I- DGND DVDD18 P1D15 P1D14 Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Clock Ground. Differential Clock Input. Differential Clock Input. Clock Ground. Clock Ground. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Analog Ground. Differential Synchronization Input. Differential Synchronization Input. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D15 (MSB). Port 1, Data Input D14. Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Rev. B | Page 14 of 56
Mnemonic P1D13 P1D12 P1D11 DGND DVDD18 P1D10 P1D9 P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 DGND DVDD18 P1D2 P1D1 P1D0
Description Port 1, Data Input D13. Port 1, Data Input D12. Port 1, Data Input D11. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D10. Port 1, Data Input D9. Port 1, Data Input D8. Port 1, Data Input D7. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D2. Port 1, Data Input D1. Port 1, Data Input D0 (LSB).
06452-004
AD9776A/AD9778A/AD9779A
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Mnemonic
DATACLK
DVDD33 TXENABLE/ IQSELECT P2D15 P2D14 P2D13 DVDD18 DGND P2D12 P2D11 P2D10 P2D9 P2D8 P2D7 P2D6 P2D5 DVDD18 DGND P2D4 P2D3 P2D2 P2D1 P2D0 DVDD18 DVDD33 SYNC_O- SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET
Description Data Clock Output. 3.3 V Digital Supply. Transmit Enable. In single port mode, this pin also functions as IQSELECT. Port 2, Data Input D15 (MSB). Port 2, Data Input D14. Port 2, Data Input D13. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D12. Port 2, Data Input D11. Port 2, Data Input D10. Port 2, Data Input D9. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D4. Port 2, Data Input D3. Port 2, Data Input D2. Port 2, Data Input D1. Port 2, Data Input D0 (LSB). 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output. Digital Ground. PLL Lock Indicator. 3-Wire Interface Port Data Output. 3-Wire Interface Port Data Input/Output. 3-Wire Interface Port Clock. 3-Wire Interface Port Chip Select Bar. Reset, Active High.
Pin No. 71 72 73
Mnemonic IRQ AGND IPTAT
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33
Description Interrupt Request. Analog Ground. Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 A at 25C with approximately 20 nA/C slope. This pin should remain floating. Voltage Reference Output. 120 A Reference Current. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. Analog Ground. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Ground. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Ground. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply.
Rev. B | Page 15 of 56
AD9776A/AD9778A/AD9779A TYPICAL PERFORMANCE CHARACTERISTICS
4 3 2 1
INL (16-BIT LSB)
100
fDATA = 160MSPS
90
fDATA = 200MSPS
-1 -2 -3 -4 -5
06452-005
SFDR (dBc)
0
80
70
fDATA = 250MSPS
60
-6
50
CODE
fOUT (MHz)
Figure 6. AD9779A Typical INL
Figure 9. AD9779A In-Band SFDR vs. fOUT, 2x Interpolation
100
1.5 1.0
fDATA = 100MSPS
90
fDATA = 200MSPS
0.5
DNL (16-BIT LSB)
0 -0.5 -1.0
SFDR (dBc)
80
fDATA = 150MSPS
70
60
-1.5 -2.0
CODE
fOUT (MHz)
Figure 7. AD9779A Typical DNL
Figure 10. AD9779A In-Band SFDR vs. fOUT, 4x Interpolation
100
100
fDATA = 50MSPS
fDATA = 100MSPS
90
fDATA = 160MSPS fDATA = 250MSPS
90
SFDR (dBc)
SFDR (dBc)
80
80
fDATA = 125MSPS
70
70
fDATA = 200MSPS
60
60
50
06452-007
fOUT (MHz)
fOUT (MHz)
Figure 8. AD9779A In-Band SFDR vs. fOUT, 1x Interpolation
Figure 11. AD9779A In-Band SFDR vs. fOUT, 8x Interpolation
Rev. B | Page 16 of 56
06452-010
0
20
40
60
80
100
50
0
10
20
30
40
50
06452-009
0
10k
20k
30k
40k
50k
60k
06452-006
50
0
20
40
60
80
100
06452-008
0
10k
20k
30k
40k
50k
60k
0
20
40
60
80
100
AD9776A/AD9778A/AD9779A
100 100
90
90
PLL OFF PLL ON
fDATA = 160MSPS
SFDR (dBc)
70
SFDR (dBc)
80
fDATA = 200MSPS
80
70
60
fDATA = 250MSPS
60
50
06452-011
fOUT (MHz)
fOUT (MHz)
Figure 12. AD9779A Out-of-Band SFDR vs. fOUT, 2x Interpolation
100 100
Figure 15. AD9779A In-Band SFDR vs. fOUT, 4x Interpolation, fDATA = 100 MSPS, PLL On/Off
0dBFS -3dBFS 90 90
SFDR (dBc)
fDATA = 150MSPS
70
SFDR (dBc)
80
80 -6dBFS 70
fDATA = 100MSPS
60
fDATA = 200MSPS
60
50
06452-012
fOUT (MHz)
fOUT (MHz)
Figure 13. AD9779A Out-of-Band SFDR vs. fOUT, 4x Interpolation
100 100
Figure 16. AD9779A In-Band SFDR vs. fOUT, Digital Full Scale
10mA 90 90 20mA
SFDR (dBc)
fDATA = 100MSPS
70
SFDR (dBc)
80
fDATA = 50MSPS
80
70 30mA
60
fDATA = 125MSPS
60
50
06452-013
fOUT (MHz)
fOUT (MHz)
Figure 14. AD9779A Out-of-Band SFDR vs. fOUT, 8x Interpolation
Figure 17. AD9779A In-Band SFDR vs. fOUT, Output Full-Scale Current
Rev. B | Page 17 of 56
06452-016
0
10
20
30
40
50
50
0
20
40
60
80
06452-015
0
20
40
60
80
100
50
0
20
40
60
80
06452-014
0
20
40
60
80
100
50
0
10
20
30
40
AD9776A/AD9778A/AD9779A
100
100
fDATA = 160MSPS
90
fDATA = 200MSPS
90
IMD (dBc)
IMD (dBc)
80
fDATA = 250MSPS
80
fDATA = 75MSPS
70
70
fDATA = 100MSPS
60
60
fDATA = 50MSPS fDATA = 125MSPS
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450
200 400
06452-020 06452-022 06452-021
50
fOUT (MHz)
06452-017
0
20
40
60
80
100
120
50
0
fOUT (MHz)
Figure 18. AD9779A Third-Order IMD vs. fOUT, 1x Interpolation
100 100
Figure 21. AD9779A Third-Order IMD vs. fOUT, 8x Interpolation
fDATA = 160MSPS
90 90
IMD (dBc)
IMD (dBc)
80
80 PLL OFF 70 PLL ON
70
fDATA = 200MSPS
60
fDATA = 250MSPS
60
50
06452-018
0
20
40
60
80
100 120 140
160 180 200
220
50
0
20
40
60
80
100
120
140
160
180
fOUT (MHz)
fOUT (MHz)
Figure 19. AD9779A Third-Order IMD vs. fOUT, 2x Interpolation
100 100 95 90 90 85 IMD (dBc) IMD (dBc) 80 80 75 70 65 60
Figure 22. AD9779A Third-Order IMD vs. fOUT, 4x Interpolation, fDATA = 100 MSPS, PLL On/Off
fDATA = 150MSPS
70
fDATA = 100MSPS
60
fDATA = 200MSPS
50 0 40 80 120 160 200 240 280 320 360 400
55 50
06452-019
0
40
80
120
160
200
240
280
320
360
fOUT (MHz)
fOUT (MHz)
Figure 20. AD9779A Third-Order IMD vs. fOUT, 4x Interpolation
Figure 23. AD9779A Third-Order IMD vs. fOUT, Over 50 Parts, 4x Interpolation, fDATA = 200 MSPS
Rev. B | Page 18 of 56
AD9776A/AD9778A/AD9779A
100 95 90 85
IMD (dBc)
REF 0dBm *PEAK Log 10dB
0dBFS -3dBFS
*ATTEN 20dB
EXT REF DC-COUPLED
80 75 70 65 60 55 50 0 40 80 120 160 200 240 280 320 360 400 -6dBFS
LGAV 51 W1 S2 S3 FC AA (f): FTUN SWP
06452-117
fOUT (MHz)
START 1.0MHz *RES BW 20kHz
VBW 20kHz
STOP 400.0MHz SWEEP 1.203s (601 pts)
Figure 24. AD9779A IMD Performance vs. fOUT, Digital Full-Scale Input Over Output Frequency, 4x Interpolation, fDATA = 200 MSPS
100
Figure 27. AD9779A Two-Tone Spectrum, 4x Interpolation, fDATA = 100 MSPS, fOUT = 30 MHz, 35 MHz
-142
95 90 20mA 85
-146 -150 -3dBFS -154 0dBFS -158 -162 -166 -170
06452-118
IMD (dBc)
80 75 70 65 60 55 50 0 40 80 120 30mA
NSD (dBm/Hz)
10mA
-6dBFS
fOUT (MHz)
fOUT (MHz)
Figure 25. AD9779A IMD Performance vs. fOUT, Full-Scale Output Current Over Output Frequency, 4x Interpolation, fDATA = 200 MSPS
REF 0dBm *PEAK log 10dB *ATTEN 20dB
Figure 28. AD9779A Noise Spectral Density vs. fOUT, Digital Full-Scale Over Output Frequency of Single-Tone Input, 2x Interpolation, fDATA = 200 MSPS
-150
EXT REF DC-COUPLED
-154
fDAC = 400MSPS
NSD (dBm/Hz) -158
fDAC = 200MSPS
LGAV 51 W1 S2 S3 FC AA (f): FTUN SWP
-162
fDAC = 800MSPS
-166
06452-023
-170
START 1.0MHz *RES BW 20kHz
VBW 20kHz
STOP 400.0MHz SWEEP 1.203s (601 pts)
fOUT (MHz)
Figure 26. AD9779A Single Tone, 4x Interpolation, fDATA = 100 MSPS, fOUT = 30 MHz
Figure 29. AD9779A Noise Spectral Density vs. fOUT, fDAC Over Output Frequency for Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS
Rev. B | Page 19 of 56
06452-026
0
20
40
60
80
100
06452-025
160
200
240
280
320
360
400
0
20
40
60
80
06452-024
AD9776A/AD9778A/AD9779A
-150
-55 -60
-154
-65
NSD (dBm/Hz)
ACLR (dBc)
-158
fDAC = 200MSPS fDAC = 400MSPS
0dBFS, PLL ENABLED -70 -75 -80 -85 0dBFS, PLL DISABLED -6dBFS, PLL DISABLED
-162
fDAC = 800MSPS
-166
-3dBFS, PLL DISABLED
-170
06452-027
fOUT (MHz)
fOUT (MHz)
Figure 30. AD9779A Noise Spectral Density vs. fOUT, fDAC Over Output Frequency with a Single-Tone Input at -6 dBFS
-55 -60 0dBFS, PLL ENABLED -65 ACLR (dBc) -70 -75 -3dBFS, PLL DISABLED -80 -6dBFS, PLL DISABLED -85 -90
Figure 33. AD9779A ACLR for Second Adjacent Band W-CDMA, 4x Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
-55 -60 -65 ACLR (dBc)
0dBFS, PLL DISABLED
-70 -6dBFS, PLL DISABLED -75 -80 -85 -90 0dBFS, PLL DISABLED 0dBFS, PLL ENABLED
-3dBFS, PLL DISABLED
06452-300
fOUT (MHz)
fOUT (MHz)
Figure 31. AD9779A ACLR for First Adjacent Band W-CDMA, 4x Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
REF -25.28dBm *AVG log 10dB *ATTEN 4dB
Figure 34. AD9779A ACLR for Third Adjacent Band W-CDMA, 4x Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
REF -30.28dBm *AVG log 10dB *ATTEN 4dB
EXT REF EXT REF
PAVG 10 W1 S2 CENTER 143.88MHz *RES BW 30kHz VBW 300kHz SPAN 50MHz SWEEP 162.2ms (601 pts)
06452-031
PAVG 10 W1 S2 CENTER 151.38MHz *RES BW 30kHz VBW 300kHz SPAN 50MHz SWEEP 162.2ms (601 pts)
LOWER dBm dBc -67.70 -85.57 -70.00 -97.87 -71.65 -99.52 UPPER dBm dBc -67.70 -85.57 -69.32 -87.19 -71.00 -88.88
RMS RESULTS FREQ OFFSET REF BW
CARRIER POWER 5.000MHz 10.00MHz -12.49dBm/ 15.00MHz 3.84000MHz 3.840MHz 3.840MHz 3.840MHz
Figure 32. AD9779A W-CDMA Signal, 4x Interpolation, fDATA = 122.88 MSPS, fDAC/4 Modulation
Rev. B | Page 20 of 56
Figure 35. AD9779A Multicarrier W-CDMA Signal, 4x Interpolation, fDAC = 122.88 MSPS, fDAC/4 Modulation
06452-032
LOWER dBm dBc -76.75 -89.23 -80.94 -93.43 -79.95 -92.44
UPPER dBm dBc -77.42 -89.91 -80.47 -92.96 -78.96 -91.45
TOTAL CARRIER POWER -12.61dBm/15.3600MHz REF CARRIER POWER -17.87dBm/3.84000MHz 1 -17.87dBm 2 -20.65dBm 3 -18.26dBm 4 -18.23dBm FREQ OFFSET 5.000MHz 10.00MHz 15.00MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz
06452-302
0
20
40
60
80 100 120 140 160 180 200 220 240 260
0
20
40
60
80 100 120 140 160 180 200 220 240 260
06452-301
0
20
40
60
80
100
-90
0
20
40
60
80 100 120 140 160 180 200 220 240 260
AD9776A/AD9778A/AD9779A
1.5
100
1.0
90
INL (14-BIT LSB)
0.5
fDATA = 160MSPS
SFDR (dBc) 80
fDATA = 200MSPS
0
fDATA = 250MSPS
70
-0.5
-1.0
60
CODE
fOUT (MHz)
Figure 36. AD9778A Typical INL
Figure 39. AD9778A In-Band SFDR vs. fOUT, 2x Interpolation
0.6 0.4 0.2
-60
DNL (14-BIT LSB)
ACLR (dBc)
0 -0.2 -0.4
-70 THIRD ADJACENT CHANNEL -80
FIRST ADJACENT CHANNEL
-0.6 -0.8 -1.0
-90
06452-034
SECOND ADJACENT CHANNEL
0
2k
4k
6k
8k CODE
10k
12k
14k
16k
fOUT (MHz)
Figure 37. AD9778A Typical DNL
Figure 40. AD9778A ACLR, Single Carrier W-CDMA, 4x Interpolation, fDATA = 122.88 MSPS, Amplitude = -3 dBFS
100
REF -25.39dBm *AVG log 10dB
*ATTEN 4dB
90 4x 150MSPS 80
IMD (dBc)
70 4x 100MSPS 60
4x 200MSPS
PAVG 10 W1 S2 CENTER 143.88MHz *RES BW 30kHz
06452-035
50
0
40
80
120
160
200
240
280
320
360
400
VBW 300kHz
SPAN 50MHz SWEEP 162.2ms (601 pts)
06452-038
fOUT (MHz)
RMS RESULTS FREQ OFFSET REF BW
CARRIER POWER 5.000MHz -12.74dBm/ 10.00MHz 3.84000MHz 15.00MHz 3.884MHz 3.840MHz 3.840MHz
LOWER dBc dBm -76.49 -89.23 -80.13 -92.87 -80.90 -93.64
UPPER dBc dBm -76.89 -89.63 -80.02 -92.76 -79.53 -92.27
Figure 38. AD9778A IMD vs. fOUT, 4x Interpolation
Figure 41. AD9778A ACLR, fDATA = 122.88 MSPS, 4x Interpolation, fDAC/4 Modulation
Rev. B | Page 21 of 56
06452-037
0
25
50
75
100
125
150
175
200
225
250
06452-036
0
2k
4k
6k
8k
10k
06452-033
-1.5
50
0
20
40
60
80
100
AD9776A/AD9778A/AD9779A
-150
0.20 0.15
-154
0.10 DNL (12-BIT LSB)
fDAC = 200MSPS
NSD (dBm/Hz) -158
0.05 0 -0.05 -0.10
fDAC = 400MSPS
-162
fDAC = 800MSPS
-166
-0.15
06452-039
0
20
40
60
80
100
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
fOUT (MHz)
Figure 42. AD9778A Noise Spectral Density vs. fOUT for Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS
-150
100 95
Figure 45. AD9776A Typical DNL
-154
90
fDAC = 200MSPS
NSD (dBm/Hz)
IMD (dBc)
85
-158
fDAC = 400MSPS
80 75 70 65 60 55 4x 150MSPS 0 40 80 120 160 200 240 280 320 360 400 4x 100MSPS 4x 200MSPS
-162
fDAC = 800MSPS
-166
-170
06452-040
fOUT (MHz)
fOUT (MHz)
Figure 43. AD9778A Noise Spectral Density vs. fOUT with Single-Tone Input at -6 dBFS, fDATA = 200 MSPS
100
Figure 46. AD9776A IMD vs. fOUT, 4x Interpolation
0.4 0.3
90 0.2 INL (12-BIT LSB) SFDR (dBc) 0.1 0 -0.1 -0.2 -0.3 -0.4 50 0 512 1024 1536 2048 CODE 2560 3072 3584 4096
06452-041
fDATA = 160MSPS
80
70
fDATA = 250MSPS fDATA = 200MSPS
60
fOUT (MHz)
Figure 44. AD9776A Typical INL
Figure 47. AD9776A In-Band SFDR vs. fOUT, 2x Interpolation
Rev. B | Page 22 of 56
06452-044
0
20
40
60
80
100
06452-043
0
20
40
60
80
100
50
06452-042
-170
-0.20
AD9776A/AD9778A/AD9779A
-55 -60 -154 -65
NSD (dBm/Hz)
-150
fDAC = 200MSPS fDAC = 400MSPS
FIRST ADJACENT CHANNEL -158 THIRD ADJACENT CHANNEL
ACLR (dBc)
-70 -75 -80 -85 -90
fDAC = 800MSPS
-162
SECOND ADJACENT CHANNEL
-166
06452-045
FOUT (MHz)
fOUT (MHz)
Figure 48. AD9776A ACLR vs. fOUT, fDATA = 122.88 MSPS, 4x Interpolation, fDAC/4 Modulation
REF -25.29dBm *AVG log 10dB *ATTEN 4dB
Figure 50. AD9776A Noise Spectral Density vs. fOUT, Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS
-150
fDAC = 200MSPS
-154
fDAC = 400MSPS
NSD (dBm/Hz)
-158
fDAC = 800MSPS
-162
PAVG 10 W1 S2 CENTER 143.88MHz *RES BW 30kHz VBW 300kHz SPAN 50MHz SWEEP 162.2ms (601 pts)
06452-046
-166
-170
RMS RESULTS FREQ OFFSET REF BW
CARRIER POWER 5.000MHz 10.00MHz -12.67dBm/ 15.00MHz 3.84000MHz 3.884MHz 3.840MHz 3.840MHz
LOWER dBm dBc -75.00 -87.67 -78.05 -90.73 -77.73 -90.41
UPPER dBm dBc -75.30 -87.97 -77.99 -90.66 -77.50 -90.17
fOUT (MHz)
Figure 49. AD9776A Single Carrier W-CDMA, 4x Interpolation, fDATA = 122.88 MSPS, Amplitude = -3 dBFS
Figure 51. AD9776A Noise Spectral Density vs. fOUT, Single-Tone Input at -6 dBFS, fDATA = 200 MSPS
Rev. B | Page 23 of 56
06452-048
0
10
20
30
40
50
60
70
80
90
100
06452-047
0
25
50
75
100
125
150
175
200
225
250
-170
0
10
20
30
40
50
60
70
80
90
100
AD9776A/AD9778A/AD9779A TERMINOLOGY
Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current at Code 0 from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error Gain error is the difference between the actual and the ideal output spans. The actual span is determined by the difference between the full-scale output and the bottom-scale output. Output Compliance Range Output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. In-Band Spurious-Free Dynamic Range (SFDR) In-band SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Out-of-Band Spurious-Free Dynamic Range (SFDR) Out-of-band SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the Nyquist frequency of the DAC output sample rate. Normally, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in dBc of the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.
Rev. B | Page 24 of 56
AD9776A/AD9778A/AD9779A THEORY OF OPERATION
The AD9776A/AD9778A/AD9779A have many features that make them highly suited for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. The speed and performance of the parts allow wider bandwidths and more carriers to be synthesized than in previously available DACs. The digital engine uses an innovative filter architecture that combines the interpolation with a digital quadrature modulator. This allows the parts to perform digital quadrature frequency upconversions. The on-chip synchronization circuitry enables multiple devices to be synchronized to each other, or to a system clock. This means that the AD9776A/AD9778A/AD9779A PLL remains in lock in a given range over a wider temperature range than the AD9776/AD9778/AD9779. See Table 23 for PLL lock ranges for the AD9776A/AD9778A/AD9779A.
PLL Optimal Settings
The optimal settings for the AD9776/AD9778/AD9779 differ from the AD9776A/AD9778A/AD9779A. Refer to the PLL Bias Settings section for complete details.
Input Data Delay Line, Manual and Automatic Correction Modes
The AD9776A/AD9778A/AD9779A can be programmed to not only sense when the timing margin on the input data falls below a preset threshold but to also take action. The device can be programmed to either set the IRQ (pin and register) or automatically reoptimize the timing input data timing.
DIFFERENCES BETWEEN AD9776/AD9778/ AD9779 AND AD9776A/AD9778A/AD9779A
REFCLK Maximum Frequency vs. Supply
With some restrictions on the DVDD18 and CVDD18 power supplies, the AD9776A/AD9778A/AD9779A support a maximum sample rate of 1100 MHz. Table 2 lists the valid operating frequencies vs. power supply voltage.
Input Data Timing
See Table 28 for timing specifications vs. temperature. The input data timing specifications (setup and hold) are different for the AD9776A/AD9778A/AD9779A than they are for the AD9776/AD9778/AD9779.
REFCLK Amplitude
With a differential sinusoidal clock applied to REFCLK, the PLL on the AD9776/AD9778/AD9779 does not achieve optimal noise performance unless the REFCLK differential amplitude is increased to 2 V p-p. Note that if an LVPECL driver is used on the AD9776/AD9778/AD9779, the PLL exhibits optimal performance if the REFCLK amplitude is well within LVPECL specifications (<1.6 V p-p differential). The design of the PLL on the AD9779A has been improved so that even with a sinusoidal clock, the PLL still achieves optimal amplitude if the swing is 1.6 V p-p.
DATACLK Delay Range
In the AD9776/AD9778/AD9779, the input data delay was controlled by Register 0x04, Bits[7:4]. At 25C, the delay was stepped by approximately 180 ps/increment. In the AD9776A/ AD9778A/AD9779A, an extra bit has been added, which effectively doubles the delay range. This bit is now located at Register 0x01, Bit 1. The increment/step on the AD9776A/AD9778A/AD9779A remains at ~180 ps.
PLL Lock Ranges
The individual lock ranges for the AD9776A/AD9778A/AD9779A PLL are wider than those for the AD9776/AD9778/AD9779.
Version Register
The version register (Register 0x1F) of the AD9776A/AD9778A/ AD9779A reads a value of 0x07. The version register of the AD9776/AD9778/AD9779 reads a value of 0x03.
Table 10. Register Value Differences Between AD9776/AD9778/AD9779 and AD9776A/AD9778A/AD9779A
Part No. AD9776/AD9778/AD9779 AD9776A/AD9778A/AD9779A PLL Loop Bandwidth, Register 0x0A, Bits[4:0] 11111 01111 PLL Bias, Register 0x09, Bits[2:0] 111 011 VCO Control Voltage, Register 0x0A, Bits[7:5] 010 011 PLL VCO Drive, Register 0x08, Bits[1:0] 00 11
Rev. B | Page 25 of 56
AD9776A/AD9778A/AD9779A 3-WIRE INTERFACE
The 3-wire port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The port is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel(R) SSR protocols. The interface allows read and write access to all registers that configure the AD9776A/AD9778A/AD9779A. Singleor multiple-byte transfers are supported, as well as MSB-first or LSB-first transfer formats. Serial data input/output can be accomplished through a single bidirectional pin (SDIO) or through two unidirectional pins (SDIO/SDO). The serial port configuration is controlled by Register 0x00, Bits[7:6]. It is important to note that any change made to the serial port configuration occurs immediately upon writing to the last bit of this byte. Therefore, it is possible with a multibyte transfer to write to this register and change the configuration in the middle of a communication cycle. Care must be taken to compensate for the new configuration within the remaining bytes of the current communication cycle. Use of a single-byte transfer when changing the serial port configuration is recommended to prevent unexpected device behavior. As described in this section, all serial port data is transferred to/from the device in synchronization with the SCLK pin. If synchronization is lost, the device has the ability to asynchronously terminate an I/O operation, putting the serial port controller into a known state and, thereby, regaining synchronization.
SDO 66 SDIO 67 SCLK 68
06452-049
A logic high on the CSB pin followed by a logic low resets the 3-wire interface port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation, regardless of the state of the internal registers or the other signal levels at the inputs to the 3-wire interface port. If the 3-wire interface port is in an instruction cycle or a data transfer cycle, none of the present data is written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte. Using one multibyte transfer is preferred. Single-byte data transfers are useful in reducing CPU overhead when register access requires only one byte. Registers change immediately upon writing to the last bit of each transfer byte.
INSTRUCTION BYTE
See Table 11 for information contained in the instruction byte. Table 11. 3-Wire Interface Instruction Byte
MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0
R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation. N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. The translation for the number of bytes to be transferred is listed in Table 12. A4, A3, A2, A1, and A0--Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0, respectively, of the instruction byte--determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the device, based on the LSB-first bit (Register 0x00, Bit 6). Table 12. Byte Transfer Count
N1 0 0 1 1 N0 0 1 0 1 Description Transfer one byte Transfer two bytes Transfer three bytes Transfer four bytes
SPI PORT
CSB 69
Figure 52. 3-Wire Interface Port
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases of a communication cycle with the AD9776A/AD9778A/AD9779A. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coinciding with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device.
Rev. B | Page 26 of 56
AD9776A/AD9778A/AD9779A
SERIAL INTERFACE PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device and controls the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first format is active. The serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations if the LSB-first format is active.
INSTRUCTION CYCLE CSB DATA TRANSFER CYCLE
Chip Select (CSB)
Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communication lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.
SCLK
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 N D5 N D30 D2 0 D1 0 D00
06452-050
SDIO
SDO
D7 D6 N D5N
D30 D20 D1 0 D00
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, configuring the SDIO pin as unidirectional.
Figure 53. Serial Register Interface Timing, MSB First
INSTRUCTION CYCLE CSB
DATA TRANSFER CYCLE
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the device operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.
SCLK
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7 N
06452-051
SDIO
SDO
D00 D10 D20
D4N D5 N D6N D7N
Figure 54. Serial Register Interface Timing, LSB First
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the LSB-/MSB-first register bit (Register 0x00, Bit 6). The default is MSB-first format (LSB/MSB first = 0). When MSB-first format is selected (LSB/MSB first = 0), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from high address to low address. In MSB-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. When LSB/MSB first = 1 (LSB first) the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte, followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle.
tDS
CSB
tSCLK
tPWH
SCLK
tPWL
tDS
SDIO
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 55. Timing Diagram for 3-Wire Interface Register Write
CSB
SCLK
06452-053
tDV
SDIO SDO DATA BIT n DATA BIT n - 1
Figure 56. Timing Diagram for 3-Wire Interface Register Read
Rev. B | Page 27 of 56
06452-052
tDH
AD9776A/AD9778A/AD9779A 3-WIRE INTERFACE REGISTER MAP
Note that all unused register bits should be kept at the device default values. Table 13.
Register Name Comm Address Hex Decimal 0x00 00 Bit 7 SDIO bidirectional Bit 6 LSB/MSB first Bit 5 Software reset Bit 3 Bit 2 Auto powerdown enable Filter Modulation Mode[3:0] Bit 4 Powerdown mode Bit 1 PLL lock indicator (read only) DATACLK Delay[4] TxEnable invert Bit 0 Def. 0x00
Digital Control
0x01
01
Interpolation Factor[1:0]
0x02
02
Data format
Single port
Real mode
Sync Control
0x03 0x04 0x05 0x06 0x07
03 04 05 06 07
DATACLK delay mode
Reserved (set to 1) DATACLK Delay[3:0] SYNC_O Delay[3:0]
DATACLK delay enable DATACLK Divide[1:0]
Inverse sinc enable
DATACLK invert
Zero stuffing enable Q first
0x00
0x00
Data Timing Margin[3:0] SYNC_O Divide[2:0] SYNC_I Ratio[2:0] SYNC_O Delay[4] SYNC_I Delay[4]
0x00 0x00 0x00 0x00 0x00
PLL Control Misc. Control I DAC Control
0x08 0x09 0x0A 0x0B 0x0C
08 09 10 11 12
SYNC_I Delay[3:0] SYNC_I Timing Margin[3:0] SYNC_O SYNC_O Clock State[4:0] enable triggering edge PLL Band Select[5:0] PLL VCO Drive[1:0] PLL enable PLL VCO Divide Ratio[1:0] PLL Loop Divide PLL Bias[2:0] Ratio[1:0] VCO Control Voltage[2:0] (read only) PLL Loop Bandwidth[4:0] SYNC_I enable I DAC Gain Adjustment[7:0] I DAC sleep I DAC powerdown Auxiliary DAC1 current direction Q DAC powerdown Auxiliary DAC2 Data[7:0] Auxiliary DAC2 sign Auxiliary DAC2 current direction Auxiliary DAC2 powerdown Reserved Auxiliary DAC2 Data[9:8] Auxiliary DAC1 Data[7:0] Auxiliary DAC1 powerdown Q DAC Gain Adjustment[7:0] I DAC Gain Adjustment[9:8]
0xE7 0x52 0x1F 0xF9 0x01
Aux DAC1 Control
0x0D 0x0E
13 14
Auxiliary DAC1 sign
Auxiliary DAC1 Data[9:8]
0x00 0x00
Q DAC Control
0x0F 0x10
15 16
Q DAC sleep
Q DAC Gain Adjustment[9:8]
0xF9 0x01
Aux DAC2 Control
0x11 0x12
17 18
0x00 0x00
Interrupt
0x13 to 0x18 0x19
19 to 24
25
Data timing error IRQ
Sync timing error IRQ
Data timing error type
Version
0x1F
31
Data timing error IRQ enable Version[7:0]
Sync timing error IRQ enable
Internal sync loopback
0x00
0x07
Rev. B | Page 28 of 56
AD9776A/AD9778A/AD9779A
Table 14. 3-Wire Interface Register Description
Register Name Comm Register Address 0x00 0x00 0x00 0x00 Bits 7 6 5 4 Parameter SDIO bidirectional LSB/MSB first Software reset Power-down mode Function 0: use SDIO pin as input data only. 1: use SDIO as both input and output data. 0: first bit of serial data is MSB of data byte. 1: first bit of serial data is LSB of data byte. Bit must be written with a 1 and then 0 to soft reset the 3-wire interface register map. 0: all circuitry is active. 1: disable all digital and analog circuitry, only 3-wire interface port is active. Controls auto power-down mode. See the PowerDown and Sleep Modes section. 0: PLL is not locked. 1: PLL is locked. 00: 1x interpolation. 01: 2x interpolation. 10: 4x interpolation. 11: 8x interpolation. See Table 19 for filter modes. Sets MSB of delay of REFCLK input to DATACLK output. 0: zero stuffing off. 1: zero stuffing on. 0: twos compliment. 1: unsigned binary. 0: both P1D and P2D data ports enabled. 1: data for both DACs received on P1D data port. 0: enable Q path for signal processing. 1: disable Q path data (internal Q channel clocks disabled, I and Q modulators disabled). Enables the DATACLK delay feature. More details on this feature are shown in the Optimizing the Data Input Timing section. 0: inverse sinc filter disabled. 1: inverse sinc filter enabled. 0: output DATACLK same phase as internal data sampling clock, DCLK_SMP signal. 1: output DATACLK opposite phase as internal data sampling clock, DCLK_SMP signal. Inverts the polarity of Pin 39, the TXENABLE input pin (also functions as IQSELECT). 0: in interleaved mode, the I data precedes the Q data on the input port. 1: in interleaved mode, the Q data precedes the I data on the input port. Default 0 0 0
0x00 0x00 Digital Control 0x01
3 1 7:6
Auto power-down enable PLL lock indicator (read only) Interpolation Factor[1:0]
0
00
0x01 0x01 0x01 0x02 0x02 0x02
5:2 1 0 7 6 5
Filter Modulation Mode[3:0] DATACLK Delay[4] Zero stuffing enable Data format Single port Real mode
0000 0 0 0 0 0
0x02
4
DATACLK delay enable
0x02 0x02
3 2
Inverse sinc enable DATACLK invert
0 0
0x02 0x02
1 0
TxEnable invert Q first
0
Rev. B | Page 29 of 56
AD9776A/AD9778A/AD9779A
Register Name Sync Control Register Address 0x03 0x03 0x03 Bits 7 6 5:4 Parameter DATACLK delay mode Reserved DATACLK Divide[1:0] Function 0: manual data timing error detect mode. 1: automatic data timing error detect mode. Should always be set to 1. DATACLK output divider value. 00: divide by 1. 01: divide by 2. 10: divide by 4. 11: divide by 1. Sets the timing margin required to prevent the data timing error IRQ bit from being asserted. Sets delay of REFCLK input to DATACLK output (see Table 29 for details). The frequency of the SYNC_O signal is equal to fDAC/N, where N is set as follows: 000: N = 32. 001: N = 16. 010: N = 8. 011: N = 4. 100: N = 2. 101: N = 1. 110: N = undefined. 111: N = undefined. The SYNC_O Delay[4:0] value programs the value of the delay line of the SYNC_O signal. The delay of SYNC_O is relative to REFCLK. The delay line resolution is 80 ps per step. 00000: nominal delay. 00001: adds 80 ps delay to SYNC_O. 00010: adds 160 ps delay to SYNC_O. ... 11111: Adds 2480 ps delay to SYNC_O. This value controls the number of SYNC_I input pulses required to generate a synchronization pulse (see Table 30 for details). The SYNC_I Delay[4:0] value programs the value of the delay line of the SYNC_I signal. The delay line resolution is 80 ps per step. 00000: nominal delay. 00001: adds 80 ps delay to SYNC_I. 00010: adds 160 ps delay to SYNC_I. ... 11111: adds 2480 ps delay to SYNC_I. 1: enables the SYNC_I input. 1: enables the SYNC_O output. 0: SYNC_O changes on REFCLK falling edge. 1: SYNC_O changes on REFCLK rising edge. This value determines the state of the internal clock generation state machine upon synchronization. Default 0 0 00
0x03 0x04 0x04
3:0 7:4 3:1
Data Timing Margin[3:0] DATACLK Delay[3:0] SYNC_O Divide[2:0]
0000 0000 000
0x04 0x05
0 7:4
SYNC_O Delay[4] SYNC_O Delay[3:0]
0 0000
0x05
3:1
SYNC_I Ratio[2:0]
000
0x05 0x06
0 7:4
SYNC_I Delay[4] SYNC_I Delay[3:0]
0 0000
0x06 0x07 0x07 0x07 0x07
3:0 7 6 5 4:0
SYNC_I Timing Margin[3:0] SYNC_I enable SYNC_O enable SYNC_O triggering edge Clock State[4:0]
0000 0 0 0 0
Rev. B | Page 30 of 56
AD9776A/AD9778A/AD9779A
Register Name PLL Control Register Address 0x08 Bits 7:2 Parameter PLL Band Select[5:0] Function Default 111001
This sets the operating frequency range of the VCO. For details (see Table 23).
Controls the signal strength of the VCO output. Set to 11 for optimal performance. 0: PLL off, DAC sample clock is sourced directly by the REFCLK input. 1: PLL on, DAC clock synthesized internally from REFCLK input via PLL clock multiplier. Sets the value of the VCO output divider, which determines the ratio of the VCO output frequency to the DAC sample clock frequency, fVCO/fDACCLK. 00: fVCO/fDACCLK = 1. 01: fVCO/fDACCLK = 2. 10: fVCO/fDACCLK = 4. 11: fVCO/fDACCLK = 8. Sets the value of the DACCLK divider, which determines the ratio of the DAC sample clock frequency to the REFCLK frequency, fDACCLK/fREFCLK. 00: fDACCLK/fREFCLK = 2. 01: fDACCLK/fREFCLK = 4. 10: fDACCLK/fREFCLK = 8. 11: fDACCLK/fREFCLK = 16. Controls VCO bias current. Set to 011 for optimal performance. 000 to 111, proportional to voltage at VCO control voltage input, readback only. A value of 011 indicates the VCO centered in its frequency range. Controls the bandwidth of the PLL filter. Increasing the value lowers the loop bandwidth. Set to 01111 for optimal performance. The I DAC Gain Adjustment[9:0] value is the I DAC 10-bit gain setting word. Bit 9 is the MSB and Bit 0 is the LSB. 0: I DAC on. 1: I DAC off, but reference remains powered. 0: I DAC on. 1: I DAC off. The auxiliary DAC 1 Data [9:0] value is the Aux DAC1 10-bit output current control word. Magnitude of the auxiliary DAC current increases with increasing value. Bit 9 is the MSB and Bit 0 is the LSB. 0: AUX1_P active. 1: AUX1_N active. 0: source. 1: sink. 0: auxiliary DAC1 on. 1: auxiliary DAC1 off. The Q DAC Gain Adjustment[9:0] value is the Q DAC 10-bit gain setting word. Bit 9 is the MSB and Bit 0 is the LSB. 0: Q DAC on. 1: Q DAC off. 0: Q DAC on. 1: Q DAC off.
0x08 0x09
1:0 7
PLL VCO Drive[1:0] PLL enable
11 0
0x09
6:5
PLL VCO Divide Ratio[1:0]
10
0x09
4:3
PLL Loop Divide Ratio[1:0]
10
0x09 Misc. Control 0x0A
2:0 7:5
PLL Bias[2:0] VCO Control Voltage[2:0] (read only) PLL Loop Bandwidth[4:0]
010 000
0x0A
4:0
11111
I DAC Control
0x0C 0x0B 0x0C 0x0C
1:0 7:0 7 6 1:0 7:0
I DAC Gain Adjustment[9:8] I DAC Gain Adjustment[7:0] I DAC sleep I DAC power-down Auxiliary DAC1 Data[9:8] Auxiliary DAC1 Data[7:0]
01 11111001 0 0 00 00000000
Aux DAC1 Control
0x0E 0x0D
0x0E 0x0E 0x0E Q DAC Control 0x10 0x0F 0x10 0x10
7 6 5 1:0 7:0 7 6
Auxiliary DAC1 sign Auxiliary DAC1 current direction Auxiliary DAC1 power-down Q DAC Gain Adjustment[9:8] Q DAC Gain Adjustment[7:0] Q DAC sleep Q DAC power-down
0 0 0 01 11111001 0 0
Rev. B | Page 31 of 56
AD9776A/AD9778A/AD9779A
Register Name AUX DAC2 Control Register Address 0x12 0x11 Bits 1:0 7:0 Parameter Auxiliary DAC2 Data[9:8] Auxiliary DAC2 Data[7:0] Function Auxiliary DAC2 Data[9:0] is the 10-bit output current control word. Magnitude of the auxiliary DAC current increases with increasing value. Bit 9 is the MSB and Bit 0 is the LSB. 0: AUX2_P active. 1: AUX2_N active. 0: source. 1: sink. 0: auxiliary DAC2 on. 1: auxiliary DAC2 off. Default 00 00000000
0x12 0x12 0x12 0x13 to 0x18 0x19
7 6 5
Auxiliary DAC2 sign Auxiliary DAC2 current direction Auxiliary DAC2 power-down Reserved
0 0 0
Interrupt
7
Data timing error IRQ
0x19
6
Sync timing error IRQ
0x19
4
Data timing error type
0x19 0x19 0x19 Version 0x1F
3 2 0 7:0
Data timing error IRQ enable Sync timing error IRQ enable Internal sync loopback Version[7:0]
Read only. Active high indicates a timing violation occurred on the input data port. The IRQ is latched. This bit is cleared when the Interrupt register is read. Read only. Active high indicates a timing violation occurred on the SYNC_I input. The IRQ is latched. This bit is cleared when the Interrupt register is read. Read only. Indicates the timing error type. 0: hold time violation. 1: setup time violation. Meaningful when data timing error IRQ is active. 0: data timing error IRQ is masked. 1: data timing error IRQ is enabled. 0: sync timing error IRQ is masked. 1: sync timing error IRQ is enabled. The received SYNC_O signal is looped back to the SYNC_I signal. Indicates device hardware revision number.
0
0
0
0 0 0 00000111
Rev. B | Page 32 of 56
AD9776A/AD9778A/AD9779A INTERPOLATION FILTER ARCHITECTURE
The AD9776A/AD9778A/AD9779A can provide up to 8x interpolation, or the interpolation filters can be entirely disabled. It is important to note that the input signal should be backed off by approximately 0.01 dB from full scale to avoid overflowing the interpolation filters. The coefficients of the low-pass filters and the inverse sinc filter are given in Table 15, Table 16, Table 17, and Table 18. Spectral plots for the filter responses are shown in Figure 57, Figure 58, and Figure 59. Table 15. Low-Pass Filter 1
Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) Upper Coefficient H(55) H(54) H(53) H(52) H(51) H(50) H(49) H(48) H(47) H(46) H(45) H(44) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) Integer Value -4 0 +13 0 -34 0 +72 0 -138 0 +245 0 -408 0 +650 0 -1003 0 +1521 0 -2315 0 +3671 0 -6642 0 +20,755 +32,768
Table 16. Low-Pass Filter 2
Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) Upper Coefficient H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) Integer Value -2 0 +17 0 -75 0 +238 0 -660 0 +2530 +4096
Table 17. Low-Pass Filter 3
Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) Upper Coefficient H(15) H(14) H(13) H(12) H(11) H(10) H(9) Integer Value -39 0 +273 0 -1102 0 +4964 +8192
Table 18. Inverse Sinc Filter
Lower Coefficient H(1) H(2) H(3) H(4) H(5)
10 0 -10 -20
ATTENUATION (dB)
Upper Coefficient H(9) H(8) H(7) H(6)
Integer Value +2 -4 +10 -35 +401
-30 -40 -50 -60 -70 -80 -90
06452-054
-100 -4
-3
-2
-1
0
1
2
3
4
fOUT (x Input Data Rate)
Figure 57. 2x Interpolation, Low-Pass Response to 4x Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off)
Rev. B | Page 33 of 56
AD9776A/AD9778A/AD9779A
10 0 -10 -20
ATTENUATION (dB) ATTENUATION (dB)
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90
06452-055
-30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4
fOUT (x Input Data Rate)
fOUT (x Input Data Rate)
Figure 58. 4x Interpolation, Low-Pass Response to 4x Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off)
Figure 61. Interpolation/Modulation Combination of 4fDAC/8 Filter
10
10 0 -10 -20
ATTENUATION (dB) ATTENUATION (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
06452-059 06452-060
-30 -40 -50 -60 -70 -80 -90
06452-056
-100 -4
-100 -4
-3
-2
-1
0
1
2
3
4
-3
-2
-1
0
1
2
3
4
fOUT (x Input Data Rate)
fOUT (x Input Data Rate)
Figure 62. Interpolation/Modulation Combination of -3fDAC/8 Filter
Figure 59. 8x Interpolation, Low-Pass Response to 4x Input Data Rate (Dotted Lines Indicate 1 dB Roll-Off)
ATTENUATION (dB)
With the interpolation filter and modulator combined, the incoming signal can be placed anywhere within the Nyquist region of the DAC output sample rate. When the input signal is complex, this architecture allows modulation of the input signal to positive or negative Nyquist regions (see Table 19). The Nyquist regions of up to 4x the input data rate can be seen in Figure 60.
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
06452-086
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4
-4
-3x
-2x
-1x
DC
1x
2x
3x
4x
Figure 60. Nyquist Zones
Figure 57, Figure 58, and Figure 59 show the low-pass response of the digital filters with no modulation. By turning on the modulation feature, the response of the digital filters can be tuned to anywhere within the DAC bandwidth. As an example, Figure 61 to Figure 67 show the nonshifted mode filter responses for 8x interpolation (refer to Table 19 for shifted/nonshifted mode filter responses).
fOUT (x Input Data Rate)
Figure 63. Interpolation/Modulation Combination of -2fDAC/8 Filter
Rev. B | Page 34 of 56
06452-058
-100 -4
-3
-2
-1
0
1
2
3
4
AD9776A/AD9778A/AD9779A
10 0 -10 -20 10 0 -10 -20
ATTENUATION (dB)
-30 -40 -50 -60 -70 -80 -90
06452-061
ATTENUATION (dB)
-3 -2 -1 0 1 2 3
-30 -40 -50 -60 -70 -80 -90
06452-064
-100 -4
4
-100 -4
-3
-2
-1
0
1
2
3
4
fOUT (x Input Data Rate)
fOUT (x Input Data Rate)
Figure 64. Interpolation/Modulation Combination of -fDAC/8 Filter
Figure 67. Interpolation/Modulation Combination of 3fDAC/8 Filter
10 0 -10 -20
-30 -40 -50 -60 -70 -80 -90
06452-062
Shifted mode filter responses allow the pass band to be centered around 0.5 fDATA, 1.5 fDATA, 2.5 fDATA, and 3.5 fDATA. Switching to the shifted mode response does not affect the center frequency of the signal. Instead, the pass band of the filter is simply shifted. For example, use the response shown in Figure 67 and assume the signal in-band is a complex signal over the bandwidth 3.2 fDATA to 3.3 fDATA. If the shifted mode filter response is then selected, the pass band becomes centered at 3.5 fDATA. However, the signal remains at the same place in the spectrum. The shifted mode capability allows the filter pass band to be placed anywhere in the DAC Nyquist bandwidth. The AD9776A/AD9778A/AD9779A are dual DACs with internal complex modulators built into the interpolating filter response. In dual channel mode, the devices expect the real and imaginary components of a complex signal at Digital Input Port 1 and Digital Input Port 2 (I and Q, respectively). The DAC outputs then represent the real and imaginary components of the input signal, modulated by the complex carrier (fDAC/2, fDAC/4, or fDAC/8). With Register 0x02, Bit 6, set, the device accepts interleaved data on Port 1 in the I, Q, I, Q ... sequence. Note that in interleaved mode, the channel data rate at the beginning of the I and Q data paths is now half the input data rate because of the interleaving. The maximum input data rate is still subject to the maximum specification of the device. This limits the synthesis bandwidth available at the input in interleaved mode. With Register 0x02, Bit 5 (the real mode bit), set, the Q channel and the internal I and Q digital modulation are turned off. The output spectrum at the I DAC then represents the signal at Digital Input Port 1, interpolated by 1x, 2x, 4x, or 8x.
fOUT (x Input Data Rate)
06452-063
ATTENUATION (dB)
-100 -4
-3
-2
-1
0
1
2
3
4
fOUT (x Input Data Rate)
Figure 65. Interpolation/Modulation Combination of fDAC/8 Filter
10 0 -10 -20
ATTENUATION (dB)
-30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4
Figure 66. Interpolation/Modulation Combination of 2fDAC/8 Filter
The general recommendation is that if the desired signal is within 0.4 x fDATA, use the nonshifted filter mode. Outside of this, the shifted filter mode should be used. In any situation, the total bandwidth of the signal is less than 0.8 x fDATA.
Rev. B | Page 35 of 56
AD9776A/AD9778A/AD9779A
Table 19. Interpolation Filter Modes, (Register 0x01, Bits[5:2])
Interpolation Factor[7:6] 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 4 4 4 4 4 4 4 2 2 2 2 Filter Modulation Mode[5:2] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x00 0x01 0x02 0x03 Modulation DC DC shifted fDAC/8 fDAC/8 shifted fDAC/4 fDAC/4 shifted 3fDAC/8 3fDAC/8 shifted fDAC/2 fDAC/2 shifted -3fDAC/8 -3fDAC/8 shifted -fDAC/4 -fDAC/4 shifted -fDAC/8 -fDAC/8 shifted DC DC shifted fDAC/4 fDAC/4 shifted fDAC/2 fDAC/2 shifted -fDAC/4 -fDAC/4 shifted DC DC shifted fDAC/2 fDAC/2 shifted Nyquist Zone Pass Band 0 +1 +2 +3 +4 +5 +6 +7 8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 4 -3 -2 -1 0 +1 2 -1 Frequency Normalized to fDAC Low Center High -0.05 0 +0.05 +0.0125 +0.0625 +0.1125 +0.075 +0.125 +0.175 +0.1375 +0.1875 +0.2375 +0.2 +0.25 +0.3 +0.2625 +0.3125 +0.3625 +0.325 +0.375 +0.425 +0.3875 +0.4375 +0.4875 -0.55 -0.5 -0.45 -0.4875 -0.4375 -0.3875 -0.425 -0.375 -0.343 -0.3625 -0.3125 -0.2625 -0.3 -0.25 -0.2 -0.2375 -0.1875 -0.1375 -0.175 -0.125 -0.075 -0.1125 -0.0625 -0.0125 -0.1 0 +0.1 +0.025 +0.125 +0.225 +0.15 +0.25 +0.35 +0.275 +0.375 +0.475 -0.6 -0.5 -0.4 -0.475 -0.375 -0.275 -0.35 -0.25 -0.15 -0.225 -0.125 -0.025 -0.2 0 +0.2 +0.05 +0.25 +0.45 -0.7 -0.5 -0.3 -0.45 -0.25 -0.05 Comments In 8x interpolation; BW (min) = 0.0375 x fDAC BW (max) = 0.1 x fDAC
In 4x interpolation; BW (min) = 0.075 x fDAC BW (max) = 0.2 x fDAC
In 2x interpolation; BW (min) = 0.15 x fDAC BW (max) = 0.4 x fDAC
Rev. B | Page 36 of 56
AD9776A/AD9778A/AD9779A
INTERPOLATION FILTER BANDWIDTH LIMITS
The AD9776A/AD9778A/AD9779A use a novel interpolation filter architecture that allows DAC IF frequencies to be generated anywhere in the spectrum. Figure 68 shows the traditional choice of DAC IF output bandwidth placement. Note that there are no possible filter modes in which the carrier can be placed near 0.5 x fDATA, 1.5 x fDATA, 2.5 x fDATA, and so on.
10 0
+fDAC /8 +fDAC /4 +fDAC /2 -fDAC /2 -fDAC /4 -fDAC /8
10
SHIFTED + 3 x fDAC /8
06452-087
SHIFTED - 3 x fDAC /8
0 -10
ATTENUATION (dB)
SHIFTED + fDAC/8
-20 -30 -40 -50 -60 -70 -80 -4
-10
ATTENUATION (dB)
-20 -30 -40 -50 -60 -70
BASEBAND
SHIFTED + fDAC/4
SHIFTED - fDAC /4
SHIFTED - fDAC /8
SHIFTED + DC
SHIFTED - DC
-3
-2
-1
0
1
2
3
4
ASSUMING 8x INTERPOLATION
fOUT (x Input Data Rate),
Figure 70. Shifted Bandwidths Accessible with the Filter Architecture
-80 -4
-3
-2
-1
0
1
2
3
4
06452-065
ASSUMING 8x INTERPOLATION
fOUT (x Input Data Rate),
Figure 68. Traditional Bandwidth Options for TxDAC Output IF
With this filter architecture, a signal placed anywhere in the spectrum is possible. However, the signal bandwidth is limited by the input sample rate of the DAC and the specific placement of the carrier in the spectrum. The bandwidth restriction resulting from the combination of filter response and input sample rate is often referred to as the synthesis bandwidth, because this is the largest bandwidth that the DAC can synthesize. The maximum bandwidth condition exists if the carrier is placed directly in the center of one of the filter pass bands. In this case, the total 0.1 dB bandwidth of the interpolation filters is equal to 0.8 x fDATA. As Table 19 shows, the synthesis bandwidth as a fraction of the DAC output sample rate drops by a factor of 2 for every doubling of interpolation rate. The minimum bandwidth condition exists, for example, if a carrier is placed at 0.25 x fDATA. In this situation, if the nonshifted filter response is enabled, the high end of the filter response cuts off at 0.4 x fDATA, thus limiting the high end of the signal bandwidth. If the shifted filter response is instead enabled, then the low end of the filter response cuts off at 0.1 x fDATA, thus limiting the low end of the signal bandwidth. The minimum bandwidth specification that applies for a carrier at 0.25 x fDATA is therefore 0.3 x fDATA. The minimum bandwidth behavior is repeated over the spectrum for carriers placed at (n 0.25) x fDATA, where n is any integer.
The filter architecture not only allows the interpolation filter pass bands to be centered in the middle of the input Nyquist zones (as explained in this section), but also allows the possibility of a 3 x fDAC/8 modulation mode when interpolating by 8. With all of these filter combinations, a carrier of given bandwidth can be placed anywhere in the spectrum and fall into a possible pass band of the interpolation filters. The possible bandwidths accessible with the filter architecture are shown in Figure 69 and Figure 70. Note that the shifted and nonshifted filter modes are all accessible by programming the filter mode for a particular interpolation rate.
10 0
BASEBAND +fDAC /8 +fDAC /4 +fDAC /2 -fDAC /2 -fDAC /4 -fDAC /8
-10
ATTENUATION (dB)
-20 -30 -40 -50 -60 -70
+3 x fDAC /8
-3 x fDAC /8
Digital Modulation
The digital quadrature modulation occurs within the interpolation filter. The modulation shifts the frequency spectrum of the incoming data by the frequency offset selected. The frequency offsets available are multiples of the input data rate. The modulation is equivalent to multiplying the quadrature input signal by a complex carrier signal, C(t), of the following form:
06452-066
-80 -4
-3
-2
-1
0
1
2
3
4
ASSUMING 8x INTERPOLATION
fOUT (x Input Data Rate),
C(t) = cos(ct) + j sin(ct)
Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture
Rev. B | Page 37 of 56
AD9776A/AD9778A/AD9779A
As shown in Table 20, the mixing functions of most of the modes result in cross-coupling of samples between the I and Q channels. The I and Q channels only operate independently with the fS/2 mode. This means that real modulation using both the I and Q DAC outputs can only be done in the fS/2 mode. All other modulation modes require complex input data and produce complex output signals. Table 20. Modulation Mixing Sequences
Modulation fDAC/2 fDAC/4 -fDAC/4 fDAC/8 Mixing Sequence I = I, -I, I, -I, ... Q = Q, -Q, Q, -Q, ... I = I, Q, -I, -Q, ... Q = Q, -I, -Q, I, ... I = I, -Q, -I, Q, ... Q = Q, I, -Q, -I, ... I = I, r(I + Q), Q, r(-I + Q), -I, -r(I + Q), -Q, r(I - Q), ... Q = Q, r(Q - I), -I, -r(Q + I), -Q, r(-Q + I), I, r(Q + I), ... where r = 2/2
Table 21. Inverse Sinc Filter
Lower Coefficient H(1) H(2) H(3) H(4) H(5) Upper Coefficient H(9) H(8) H(7) H(6) N/A Integer Value +2 -4 +10 -35 +401
The inverse sinc filter is disabled by default. It can be enabled by setting the inverse sinc enable bit (Bit 3) in Register 0x02.
0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0
06452-088
SINC-1 RESPONSE
(dB)
COMBINED SINC AND SINC -1 RESPONSE
INVERSE SINC FILTER
The inverse sinc filter is implemented as a nine-tap FIR filter. It is designed to provide less than 0.05 dB pass-band ripple up to a frequency of 0.4 x fDATA. To provide the necessary gain at the upper end of the pass band, the inverse sinc filter has an intrinsic insertion loss of 3.4 dB. The transfer function is shown in Figure 71 and the tap coefficients are given in Table 21.
-4.5
0
0.05
0.10
0.15
0.20 0.25 0.30 f/fSAMPLE
0.35
0.40
0.45
0.50
Figure 71. Transfer Function of Inverse Sinc Filter with the DAC sin(x)/x Output
Rev. B | Page 38 of 56
AD9776A/AD9778A/AD9779A SOURCING THE DAC SAMPLE CLOCK
The AD9776A/AD9778A/AD9779A offer two modes of sourcing the DAC sample clock (DACCLK). The first mode employs an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency, most commonly the data input frequency. The on-chip PLL then multiplies the reference clock up to a higher frequency, which can then be used to generate all of the internal clocks required by the DAC. The clock multiplier provides a high quality clock that meets the performance requirements of most applications. Using the on-chip clock multiplier removes the burden of generating and distributing the high speed DACCLK at the board level. The second mode bypasses the clock multiplier circuitry and allows DACCLK to be directly sourced through the REFCLK pins. This mode enables the user to source a very high quality input clock directly to the DAC core. Sourcing the DACCLK directly through the REFCLK pins may be necessary in demanding applications that require the lowest possible DAC output noise at higher output frequencies. In either case (that is, using the on-chip clock multiplier or sourcing the DACCLK directly though the REFCLK pins), it is necessary that the REFCLK signal have low jitter to maximize the DAC noise performance. The clock multiplier circuit operates such that the VCO outputs a frequency, fVCO, equal to the REFCLK input signal frequency multiplied by N1 x N2.
f VCO = f REFCLK x (N1 x N2)
The DAC sample clock frequency, fDACCLK, is equal to
f DACCLK = f REFCLK x N2
When the PLL is enabled, the maximum input clock frequency fREFCLK is 250 MHz. The values of N1 and N2 must be chosen to keep fVCO in the optimal operating range of 1.0 GHz to 2.0 GHz. Once the VCO output frequency is known, the correct PLL band select (Register 0x08, Bits[7:2]) value can be chosen.
PLL Bias Settings
There are three bias settings for the PLL circuitry that should be programmed to their nominal values. The PLL values shown in Table 22 are the recommended settings for these parameters. Table 22. PLL Settings
PLL 3-Wire Interface Control PLL Loop Bandwidth PLL VCO Drive PLL Bias Address Register Bits 0x0A [4:0] 0x08 [1:0] 0x09 [2:0] Optimal Setting 01111 11 011
DIRECT CLOCKING
When the PLL is disabled (Register 0x09, Bit 7 = 0), the REFCLK input is used directly as the DAC sample clock (DACCLK). The frequency of REFCLK needs to be the input data rate multiplied by the interpolation factor (and by an additional factor of 2 if zero stuffing is enabled).
CLOCK MULTIPLICATION
When the PLL is enabled (Register 0x09, Bit 7 = 1), the clock multiplication circuit generates the DAC sample clock from the lower rate REFCLK input. The functional diagram of the clock multiplier is shown in Figure 72.
PIN 65 AND 0x00[1] PLL LOCK DETECT PHASE DETECTOR LOOP FILTER ADC 0x0A[7:5] PLL CONTROL VOLTAGE 0x08[7:2] VCO BAND SELECT
The PLL loop bandwidth variable configures the bandwidth of the PLL loop filter. A setting of 00000 configures the bandwidth to be approximately 1 MHz. A setting of 11111 configures the bandwidth to be approximately 10 MHz. The optimal value of 01111 sets the loop bandwidth to be approximately 3 MHz.
Configuring the PLL Band Select Value
The PLL VCO has a valid operating range from approximately 1.0 GHz to 2.0 GHz. This range is covered in 63 overlapping frequency bands, as shown in Table 23. For any desired VCO output frequency, there are multiple valid PLL band select values. It is important to note that the data shown in Table 23 is for a typical device. Device-to-device variations can shift the actual VCO output frequency range by 30 MHz to 40 MHz. In addition, the VCO output frequency varies as a function of temperature. Therefore, it is required that the optimal PLL band select value be determined for each individual device at a particular operating temperature. The device has an automatic PLL band select feature on chip. When this feature is enabled, the device determines the optimal PLL band setting for the device at the given temperature. This setting holds for a 60C temperature swing in ambient temperature. If the device is operated in an environment that experiences a larger temperature swing, an offset should be applied to the automatically selected PLL band.
REFCLK (PIN 5, PIN 6)
VCO
/N2 0x09[4:3] PLL LOOP DIVISOR
/N1 0x09[6:5] PLL VCO DIVISOR /IF DATACLK OUT (PIN 37)
DACCLK
Figure 72. Clock Multiplier Circuit
Rev. B | Page 39 of 56
06452-092
0x09[7] PLL ENABLE
0x01[7:6] INTERPOLATION FACTOR
AD9776A/AD9778A/AD9779A
Table 23. Typical VCO Frequency Range vs. PLL Band Select Value
PLL Lock Ranges Over Temperature, -40C to +85C VCO Frequency Range (MHz) PLL Band Select fLOW fHIGH 111111 (63) Auto mode 111110 (62) 1975 2026 111101 (61) 1956 2008 111100 (60) 1938 1992 111011 (59) 1923 1977 111010 (58) 1902 1961 111001 (57) 1883 1942 111000 (56) 1870 1931 110111 (55) 1848 1915 110110 (54) 1830 1897 110101 (53) 1822 1885 110100 (52) 1794 1869 110011 (51) 1779 1853 110010 (50) 1774 1840 110001 (49) 1748 1825 110000 (48) 1729 1810 101111 (47) 1730 1794 101110 (46) 1699 1780 101101 (45) 1685 1766 101100 (44) 1684 1748 101011 (43) 1651 1729 101010 (42) 1640 1702 101001 (41) 1604 1681 101000 (40) 1596 1658 100111 (39) 1564 1639 100110 (38) 1555 1606 100101 (37) 1521 1600 100100 (36) 1514 1575 100011 (35) 1480 1553 100010 (34) 1475 1529 100001 (33) 1439 1505 100000 (32) 1435 1489 PLL Lock Ranges Over Temperature, -40C to +85C VCO Frequency Range (MHz) PLL Band Select fLOW fHIGH 011111 (31) 1402 1468 011110 (30) 1397 1451 011101 (29) 1361 1427 011100 (28) 1356 1412 011011 (27) 1324 1389 011010 (26) 1317 1375 011001 (25) 1287 1352 011000 (24) 1282 1336 010111 (23) 1250 1313 010110 (22) 1245 1299 010101 (21) 1215 1277 010100 (20) 1210 1264 010011 (19) 1182 1242 010010 (18) 1174 1231 010001 (17) 1149 1210 010000 (16) 1141 1198 001111 (15) 1115 1178 001110 (14) 1109 1166 001101 (13) 1086 1145 001100 (12) 1078 1135 001011 (11) 1055 1106 001010 (10) 1047 1103 001001 (9) 1026 1067 001000 (8) 1019 1072 000111 (7) 998 1049 000110 (6) 991 1041 000101 (5) 976 1026 000100 (4) 963 1011 000011 (3) 950 996 000010 (2) 935 981 000001 (1) 922 966 000000 (0) 911 951
Rev. B | Page 40 of 56
AD9776A/AD9778A/AD9779A
Configuring PLL Band Select with Temperature Sensing
The following procedure outlines a method for setting the PLL band select value for a device operating at a particular temperature that holds for a change in ambient temperature over the total -40C to +85C operating range of the device without further user intervention. Note that REFCLK must be applied to the device during this procedure. 1. Program the values of N1 (Register 0x09, Bits[6:5]) and N2 (Register 0x09, Bits[4:3]), along with the PLL settings shown in Table 22. Set the PLL band (Register 0x08, Bits[7:2]) to 63 to enable PLL auto mode. Wait for the PLL_LOCK pin or the PLL lock indicator (Register 0x00, Bit 1) to go high. This should occur within 5 ms. Read back the 6-bit PLL band (Register 0x08, Bits[7:2]). Based on the temperature when the PLL auto band select is performed, set the PLL band indicated in either Table 24 or Table 25 by rewriting the readback values into the PLL Band Select parameter (Register 0x08, Bits[7:2]).
Known Temperature Calibration with Memory
If temperature sensing is not available in the system, a factory calibration at a known temperature is another method for guaranteeing lock over temperature. Factory calibration can be performed as follows: 1. Program the values of N1 (Register 0x09, Bits[6:5]) and N2 (Register 0x09, Bits[4:3]), along with the PLL settings shown in Table 22. Set the PLL band (Register 0x08, Bits[7:2]) to 63 to enable PLL auto mode. Wait for the PLL_LOCK pin or the PLL lock indicator (Register 0x00, Bit 1) to go high. This should occur within 5 ms. Read back the 6-bit PLL band (Register 0x08, Bits[7:2]). Based on the temperature when the PLL auto band select is performed, store into nonvolatile memory the PLL band indicated in either Table 24 or Table 25. On system powerup or restart, load the stored PLL band value into the PLL band select parameter (Register 0x08, Bits[7:2]).
2. 3.
2. 3.
4. 5.
4. 5.
Set-and-Forget Device Option
If the PLL band select configuration methods described in the previous sections cannot be implemented in a particular system, there may be a screened device option that can satisfy the system requirements. This allows the user to preload a specific PLL band select value for all devices that holds over temperature. Example REFCLK and VCO frequencies are shown in Table 26. Table 26. Typical VCO Frequency Range vs. PLL Band Select Value
fREFCLK (MHz) 59.73335 61.44 67.2 76.8 80.01 81.92 92.16 112.0 119.4667 122.88 fVCO (MHz) 955.7336 1966.08 1075.2 1228.8 1280 1310.72 1474.56 1792.0 955.7336 1966.08 Guaranteed PLL Band 2 61 11 20 23 25 34 50 2 61 Total PLL Divide Ratio 16 32 16 16 16 16 16 16 8 16
This procedure requires temperature sensing upon start-up or reset of the device to optimally choose the PLL band select value that holds over the entire operating temperature range. If the optimal band is in the range of 0 to 31 (lower VCO frequency), refer to Table 24. Table 24. Setting Optimal PLL Band, When Band Is in the Lower Range (0 to 31)
If System Startup Temperature Is -40C to -10C -10C to +15C 15C to 55C 55C to 85C Set PLL Band as Follows Set PLL band = readback band + 2 Set PLL band = readback band + 1 Set PLL band = readback band Set PLL band = readback band - 1
If the optimal band is in the range of 32 to 62 (higher VCO frequency), refer to Table 25. Table 25. Setting Optimal PLL Band, When Band Is in the Higher Range (32 to 62)
If System Startup Temperature Is -40C to -30C -30C to -10C -10C to +15C 15C to 55C 55C to 85C Set PLL Band as Follows Set PLL band = readback band + 3 Set PLL band = readback band + 2 Set PLL band = readback band + 1 Set PLL band = readback band Set PLL band = readback band - 1
Rev. B | Page 41 of 56
AD9776A/AD9778A/AD9779A
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal. The signal level can range from 400 mV p-p differential to 1.6 V p-p differential centered about a 400 mV input commonmode voltage. Looking at the single-ended inputs, REFCLK+ or REFCLK-, each input pin can safely swing from 200 mV p-p to 800 mV p-p about the 400 mV common-mode voltage. Although these input levels are not directly LVDS compatible, REFCLK can be driven by an offset ac-coupled LVDS signal, as shown in Figure 73.
0.1F LVDS_P_IN 50 VCM = 400mV 50 LVDS_N_IN 0.1F REFCLK-
06452-068
TTL OR CMOS CLK INPUT
0.1F
50
REFCLK+
VCM = 400mV
Figure 74. TTL or CMOS REFCLK Drive Circuit
REFCLK+
A simple bias network for generating VCM is shown in Figure 75. It is important to use CVDD18 and CGND for the clock bias circuit. Any noise or other signal that is coupled onto the clock is multiplied by the DAC digital input signal and can degrade DAC performance.
VCM = 400mV CVDD18
1k 287 0.1F
1nF CGND
06452-070
Figure 73. LVDS REFCLK Drive Circuit
1nF
If a clean sine clock is available, it can be transformer-coupled to REFCLK, as shown in Figure 73. Use of a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through a CMOS to LVDS translator, and then ac-coupled as described in this section. Alternatively, it can be transformercoupled and clamped, as shown in Figure 74.
Figure 75. REFCLK VCM Generator Circuit
Rev. B | Page 42 of 56
06452-069
REFCLK- 50 BAV99ZXCT HIGH SPEED DUAL DIODE
AD9776A/AD9778A/AD9779A FULL-SCALE CURRENT GENERATION
INTERNAL REFERENCE
Full-scale current on the I DAC and Q DAC can be set from 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external resistor connected to I120 (Pin 75). A simplified block diagram of the reference circuitry is shown in Figure 76. The recommended value for the external resistor is 10 k, which sets up an IREFERENCE in the resistor of 120 A, which in turn provides a DAC output full-scale current of 20 mA. Because the gain error is a linear function of this resistor, a high precision resistor improves gain matching to the internal matching specification of the devices. Gain drift over temperature is also affected by this resistor. A resistor with a low temperature coefficient is recommended in applications requiring good gain stability. Internal current mirrors provide a current-gain scaling, where the I DAC or Q DAC gain is a 10-bit word in the 3-wire interface port register (Register 0x0B, Register 0x0C, Register 0x0F, and Register 0x10). The default value for the DAC gain registers gives an IFS of approximately 20 mA. IFS is equal to
VREF 0.1F I120 10k Q DAC GAIN CURRENT SCALING
AD9776A/AD9778A/AD9779A
I DAC GAIN 1.2V BAND GAP I DAC DAC FULL-SCALE REFERENCE CURRENT Q DAC
06452-073
Figure 76. Reference Circuitry
35 30 25 20 15 10 5 0
I FS =
0
200
400
600
800
1000
DAC GAIN CODE
Figure 77. IFS vs. DAC Gain Code
Rev. B | Page 43 of 56
06452-074
1.2 V 27 6 x + x DAC Gain x 32 12 1024 R
IFS (mA)
AD9776A/AD9778A/AD9779A GAIN AND OFFSET CORRECTION
Analog quadrature modulators make it very easy to realize single sideband radios. However, there are several nonideal aspects of quadrature modulator performance. Among these analog degradations are
*
scale (10-bit values, 3-wire interface Register 0x0D and 3-wire interface Register 0x11). This results in a full-scale current of approximately 2 mA for auxiliary DAC1 and auxiliary DAC2. The auxiliary DAC structure is shown in Figure 78. Only one of the two output pins of the auxiliary DAC is active at a time. The inactive side goes to a high impedance state (>100 k). The active output pin is chosen by writing to Bit 7 of Register 0x0E and Register 0x12. The active output can act as either a current source or a current sink. When sourcing current, the output compliance voltage is 0 V to 1.6 V. When sinking current, the output compliance voltage is 0.8 V to 1.6 V. The output pin is chosen to be a current source or current sink by writing to Bit 6 of Register 0x0E and Register 0x12.
0mA TO 2mA (SOURCE) VBIAS AUXP
Gain mismatch: The gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. This leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect. Local oscillator (LO) feedthrough: The quadrature modulator has a finite dc-referred offset, as well as coupling from its LO port to the signal inputs. These can lead to significant spectral spurs at the frequency of the quadrature modulator LO.
*
The AD9776A/AD9778A/AD9779A have the capability to correct for both of these analog degradations. Note that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting for them may be necessary.
0mA TO 2mA (SINK) SOURCE/ SINC
AUXN
06452-303
P/N
Figure 78. Auxiliary DAC Source/Sink for AD9776A/AD9778A/AD97779A
I/Q CHANNEL GAIN MATCHING
Gain matching is achieved by adjusting the values in the DAC gain registers. For the I DAC, these values are in the 0x0B and 0x0C I DAC control registers. For the Q DAC, these values are in the 0x0F and 0x10 Q DAC control registers. These are 10-bit values. To perform gain compensation, raise or lower the value of one of these registers by a fixed step size and measure the amplitude of the unwanted image. If the unwanted image is increasing in amplitude, stop the procedure and try the same adjustment on the other DAC control register. Do this until the image rejection cannot be improved through further adjustment of these registers. It should be noted that LO feedthrough compensation is independent of gain. However, gain compensation can affect the LO compensation because the gain compensation may change the common-mode level of the signal. The dc offset of some modulators is common-mode level dependent. Therefore, it is recommended that the gain adjustment be performed prior to LO compensation.
The magnitude of the auxiliary DAC1 current is controlled by the 0x0D and 0x0E auxiliary DAC1 control registers; the magnitude of the auxiliary DAC2 current is controlled by the 0x11 and 0x12 auxiliary DAC2 control registers. These auxiliary DACs have the ability to source or sink current. This is programmable via Bit 6 in either auxiliary DAC control register. The choice of sinking or sourcing should be made at circuit design time. There is no advantage to switching between current source or current sink once the circuit is in place. The auxiliary DACs can be used for LO cancellation when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input-referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and may degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 79. Often, the input common-mode voltage for the modulator is much higher than the output compliance range of the DAC, making ac coupling or a dc level shift necessary. If the required common-mode input voltage on the quadrature modulator matches that of the DAC, then the dc shown in Figure 79 can be used. A low-pass or band-pass passive filter is recommended when spurious signals from the DAC (distortion and DAC images) at the quadrature modulator inputs may affect the system performance. Placing the filter at the location shown in Figure 79 allows easy design of the filter because the source and load impedances can easily be designed close to 50 .
AUXILIARY DAC OPERATION
Two auxiliary DACs are provided on the AD9776A/AD9778A/ AD9779A. The full-scale output current on these DACs is derived from the 1.2 V band gap reference and external resistor between the I120 pin and ground. The gain scale from the reference amplifier current (IREFERENCE) to the auxiliary DAC reference current is 16.67 mA with the auxiliary DAC gain set to full
Rev. B | Page 44 of 56
AD9776A/AD9778A/AD9779A
90 AUX1_P
RESULTS OF GAIN AND OFFSET CORRECTION
250 LPI 390nH 39pF C2I LNI 390nH RSLI 100 22 82pF C3I IBBN 21
AD9779A
OUT1_P
500 93 RBIP 50 RBIN 92 50 250
IBBP
82pF C1I
OUT1_N
AUX1_N
89 500
The results of gain and offset correction can be seen in Figure 80 and Figure 81. Figure 80 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 81 shows the output spectrum after correction. The LO feedthrough spur at 2.1 GHz has been suppressed to the noise level. This result can be achieved by applying the correction, but the correction needs to be repeated after a large change in temperature. Note that the gain matching improved the negative frequency image rejection, but there is still a significant image present. The remaining image is now due to phase mismatch in the quadrature modulator. Phase mismatch can be distinguished from gain mismatch by the shape of the image. Note that the image in Figure 80 is relatively flat and the image in Figure 81 slopes down with frequency. Phase mismatch is frequency dependent, so an image dominated by phase mismatch has this sloping characteristic.
0
REF LVL 0dBm RBW VBW SWT 3kHz 3kHz 56s REF ATT MIXER UNIT 30dB -40dBm dBm
AUX2_N
87 500 250 LNQ 390nH
OUT2_N
84 RBQN 50 RBQP 83 50 250 82pF C3Q 82pF C1Q
9 RSLQ 100 10
QBBN
39pF C2Q LPQ 390nH
OUT2_P
QBBP
06452-093
AUX2_P
86
500
Figure 79. Typical Use of Auxiliary DACs AC Coupling to Quadrature Modulator
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 CENTER 2.1GHz 20MHz SPAN 200MHz
06452-304 06452-305
LO FEEDTHROUGH COMPENSATION
The LO feedthrough compensation is the most complex of all three operations. This is due to the structure of the offset auxiliary DACs, as shown in Figure 78. To achieve LO feedthrough compensation in a circuit, each of four outputs of these auxiliary DACs can be connected through a 500 resistor to ground and through a 250 resistor to one of the four quadrature modulator signal inputs. The purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, therefore adding a slight dc bias to one of the quadrature modulator signal inputs. To achieve LO feedthrough compensation, the user should start with the default conditions of the auxiliary DAC sign registers, and then increment the magnitude of one or the other auxiliary DAC output currents. While this is being done, the amplitude of the LO feedthrough at the quadrature modulator output should be sensed. If the LO feedthrough amplitude increases, try either changing the sign of the auxiliary DAC being adjusted or adjusting the output current of the other auxiliary DAC. It may take practice before an effective algorithm is achieved. Using the AD9776A/AD9778A/AD9779A evaluation board, the LO feedthrough can typically be adjusted down to the noise floor, although this is not stable over temperature.
Figure 80. AD9779A and ADL5372 with a Multitone Signal at 2.1 GHz, No Gain or LO Compensation
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
REF LVL 0dBm
RBW VBW SWT
20kHz 20kHz 1.25s
REF ATT MIXER UNIT
20dB -40dBm dBm
CENTER 2.1GHz
20MHz
SPAN 200MHz
Figure 81. AD9779A and ADL5372 with a Multitone Signal at 2.1 GHz, Gain and LO Compensation Optimized
Rev. B | Page 45 of 56
AD9776A/AD9778A/AD9779A INPUT DATA PORTS
The AD9776A/AD9778A/AD9779A can operate in two data input modes: dual port mode and single port mode. For the default dual port mode (single port bit = 0), each DAC receives data from a dedicated input port. In single port mode (single port bit = 1), both DACs receive data from Port 1. In single port mode, DAC1 and DAC2 data is interleaved, and the TXENABLE input is used to steer data to the intended DAC. In dual port mode, the TXENABLE input is used to power down the digital data path. In dual port mode, the data must be delivered at the input data rate. In single port mode, data must be delivered at twice the input data rate of each DAC. Because the data inputs function up to a maximum of 300 MSPS, it is practical to operate with input data rates up to 150 MHz per DAC in single port mode. In dual port and single port modes, a data clock output (DATACLK) signal is available as a fixed time base with which to drive data from an FPGA or other data source. This output signal operates at the input data rate.
DUAL PORT MODE
In dual port mode, data for each DAC is received on the respective input bus (P1D[15:0] or P2D[15:0]). I and Q data arrive simultaneously and are sampled on the rising edge of the DATACLK signal. The TXENABLE signal must be high to enable the transmit path.
INPUT DATA REFERENCED TO DATACLK
The simplest method of interfacing to the AD9776A/AD9778A/ AD9779A is when the input data is referenced to the DATACLK output. The DATACLK output is a buffered version (with some fixed delay) of the internal clock that is used to latch the input data. Therefore, if setup and hold times of the input data with respect to DATACLK are met, the input data is latched correctly. Detailed timing diagrams for the single and dual port cases using DATACLK as the timing reference are shown in Figure 82.
DATACLK
SINGLE PORT MODE
In single port mode, data for both DACs is received on the Port 1 input bus (P1D[15:0]). I and Q data samples are interleaved and are sampled on the rising edges of DATACLK. Along with the data, a framing signal must be supplied on the TXENABLE input (Pin 39), which steers incoming data to its respective DAC. When TXENABLE is high, the corresponding data-word is sent to the I DAC. When TXENABLE is low, the corresponding data is sent to the Q DAC. The timing of the digital interface in interleaved mode is shown in Figure 83. The Q first bit (Register 0x02, Bit 0) controls the pairing order of the input data. With the Q first bit set to the default of 0, the I-Q pairing sent to the DACs is the two input data-words corresponding to TXENABLE low followed by TXENABLE high. With the Q first bit set to 1, the I-Q pairing sent to the DACs is the two input data-words corresponding to TXENABLE high, followed by TXENABLE low. Note that with either order pairing, the data sent with TXENABLE high is directed to the I DAC, and the data sent with TXENABLE low is directed to the Q DAC.
DATACLK P1D[15:0] TXENABLE I DAC[15:0] Q FIRST = 0 Q DAC[15:0] I DAC[15:0] Q FIRST = 1 Q DAC[15:0] P1D0 P1D1 P1D2 P1D1
P1D1 P1D2 P1D3 P1D4
DATA
Figure 82. Input Data Port Timing, Data Referenced to DATACLK
Table 28 shows the setup and hold time requirements for the input data over the operating temperature range of the device. Also shown is the keep out window (KOW). The keep out window is the sum of the setup and hold times of the interface. This is the minimum amount of time valid data must be presented to the device to ensure proper sampling.
DATACLK Frequency Settings
The DATACLK signal is derived from the internal DAC sample clock, DACCLK. The frequency of the DATACLK output depends on several programmable settings. Normally, the frequency of DATACLK is equal to the input data rate. The relationship between the frequency of DACCLK and DATACLK is
f DATACLK = f DACCLK IF x ZS x SP x DATACLKDIV
where the variables IF, ZS, SP, and DATACLKDIV have the values shown in Table 27.
P1D5
P1D6
P1D7
P1D8
P1D3 P1D4 P1D3 P1D2
P1D5 P1D6
06452-306
P1D5 P1D4
Figure 83. Single Port Mode Digital Interface Timing
Rev. B | Page 46 of 56
06452-308
tSDATACLK
tHDATACLK
AD9776A/AD9778A/AD9779A
The DATACLKDIV only affects the DATACLK output frequency, not the frequency of the data sampling clock. To maintain an fDATACLK frequency that samples the input data that remains consistent with the expected data rate, DATACLKDIV should be set to 00.
Table 27. DACCLK to DATACLK Divisor Values
Variable IF ZS SP DATACLKDIV Value Interpolation factor (1, 2, 4, or 8) 1, if zero stuffing is disabled 2, if zero stuffing is enabled 0.5, if single port is enabled 1, if dual port is selected 1, 2, or 4 Address Register Bit 0x01 [7:6] 0x01 0x02 0x03 [0] [6] [5:4]
DATA SYNC_I
tH_SYNC tS_SYNC
REFCLK
tSREFCLK
Figure 84. Input Data Port Timing, Data Referenced to REFCLK, fDACCLK = fREFCLK
INPUT DATA REFERENCED TO REFCLK
In some systems, it may be more convenient to use the REFCLK input than the DATACLK output as the input data timing reference. If the frequency of DACCLK is equal to the frequency of the data input (without interpolation), then the data with respect to REFCLK timing specifications in Table 28 apply directly without further considerations. If the frequency of DACCLK is greater than the frequency of the input data, a divider is used to generate the DATACLK output (and the internal data sampling clock). This divider creates a phase ambiguity between REFCLK and DATACLK, which results in uncertainty in the sampling time. To establish fixed setup and hold times of the data interface, this phase ambiguity must be eliminated. To eliminate the phase ambiguity, the SYNC_I input pins (Pin 13 and Pin 14) must be used to force the data to be sampled on a specific REFCLK edge. The relationship among REFCLK, SYNC_I, and input data is shown in Figure 84 and Figure 85. Therefore, both SYNC_I and data must meet the timing in Table 28 for reliable data transfer into the device.
Note that even though the setup and hold times of SYNC_I are relative to REFCLK, the SYNC_I input is sampled at the internal DACCLK rate. In the case where the PLL is employed, SYNC_I must be asserted to meet the setup time with respect to REFCLK (tS_SYNC), but cannot be asserted prior to the previous rising edge of the internal SYNC_I sample clock. In other words, the SYNC_I assert edge has to be placed between its successive keep out windows that replicate at the DACCLK rate, not the REFCLK rate. The valid window for asserting SYNC_I is shaded gray in Figure 85 for the case where the PLL provides a DACCLK frequency of four times the REFCLK frequency. Thus, the minimum setup time is tS_SYNC, and the maximum setup time is tDACCLK - tH_SYNC.
tDACCLK
SYNC_I
tH_SYNC tS_SYNC
REFCLK
DACCLK
tSREFCLK
DATA
Figure 85. Input Data Port Timing, Data Referenced to REFCLK, fDACCLK = fREFCLK x 4
More details of the synchronization circuitry are found in the Device Synchronization section of this data sheet.
Table 28. Data Timing Specifications vs. Temperature
Timing Parameter Data with Respect to REFCLK Temperature -40C +25C +85C -40C to +85C -40C +25C +85C -40C to +85C -40C +25C +85C -40C to +85C Min tS (ns) -0.80 -1.00 -1.10 -0.80 2.50 2.70 3.00 3.00 0.30 0.25 0.15 0.30 PLL Disabled Min tH (ns) Min KOW (ns) 3.35 2.55 3.50 2.50 3.80 2.70 3.80 3.00 -0.05 2.45 -0.20 2.50 -0.40 2.60 -0.05 2.95 0.65 0.95 0.75 1.00 0.90 1.05 0.90 1.20 Min tS (ns) -0.83 -1.06 -1.19 -0.83 2.50 2.70 3.00 3.00 0.27 0.19 0.06 0.27 PLL Enabled Min tH (ns) Min KOW (ns) 3.87 2.99 4.04 2.98 4.37 3.16 4.37 3.54 -0.05 2.45 -0.20 2.50 -0.40 2.60 -0.05 2.95 1.17 1.39 1.29 1.48 1.47 1.51 1.47 1.74
Data with Respect to DATACLK
SYNC_I to REFCLK
Rev. B | Page 47 of 56
06452-310
tHREFCLK
06452-309
tHREFCLK
AD9776A/AD9778A/AD9779A
OPTIMIZING THE DATA INPUT TIMING
The AD9776A/AD9778A/AD9779A have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP (the internal clock that samples the input data). This optimization is made by a sequence of 3-wire interface register read and write operations. The timing optimization can be done under strict control of the user, or the device can be programmed to maintain a configurable timing margin automatically. This function is only available when the input data is referenced to the DATACLK output. Each of these methods is detailed in the following section. Figure 86 shows the circuitry that detects sample timing errors and adjusts the data interface timing. The DCLK_SMP signal is the internal clock used to latch the input data. Ultimately, it is the rising edge of this signal that needs to be centered in the valid sampling period of the input data. This is accomplished by adjusting the time delay, tD, which changes the DATACLK timing and, as a result, the arrival time of the input data with respect to DCLK_SMP.
tM TIMING MARGIN[3:0] PD1[0] D CLK Q TIMING ERROR DETECTION Q TIMING ERROR IRQ TIMING ERROR TYPE
In addition to setting the data timing error IRQ, the data timing error type bit is indicated when an error occurs. The data timing error type bit is set low to indicate a hold error and high to indicate a setup error. Figure 87 shows a timing diagram of the data interface and the status of the data timing error type bit.
DATA TIMING ERROR = 0 tM tM
DATA TIMING ERROR = 1 DATA TIMING ERROR TYPE = 1
tM DATA
tM
tM DELAYED DATA SAMPLING
tM
TIMING ERROR = 1 DATA TIMING ERROR TYPE = 0 DELAYED CLOCK SAMPLING
Figure 87. Timing Diagram of Margin Test Data
Automatic Timing Optimization
When automatic timing optimization mode is enabled (Register 0x03, Bit 7 = 1), the device continuously monitors the data timing error IRQ and data timing error type bits. The DATACLK Delay[3:0] is increased if a setup error is detected and decreased if a hold error is detected. The value of the DATACLK Delay[3:0] setting currently in use can be read back by the user.
06452-402
D tM CLK
DATACLK DELAY[3:0] DCLK_SMP tD DATACLK
Manual Timing Optimization
When the device is operating in manual timing optimization mode (Register 0x03, Bit 7 = 0), the device does not alter the DATACLK Delay[3:0] value from what is programmed by the user. By default, the DATACLK delay enable bit is inactive. This bit must be set high for the DATACLK Delay[3:0] value to be realized. The delay (in absolute time) when programming DATACLK delay between 00000 and 11111 varies from about 700 ps to about 6.5 ns. The typical delays per increment over temperature are shown in Table 29.
Table 29. Data Delay Line Typical Delays Over Temperature
Delay Zero Code Delay (Delay Upon Enabling Delay Line) Average Unit Delay -40C 630 175 +25C 700 190 +85C 740 210 Unit ps ps
Figure 86. Timing Error Detection and Optimization Circuitry
The error detect circuitry works by creating two sets of sampled data (referred to as the margin test data) in addition to the actual sampled data used in the device data path. One set of sampled data is latched before the actual data sampling point. The other set of sampled data is latched after the actual data sampling point. If the margin test data match the actual data, the sampling is considered valid and no error is declared. If there is a mismatch between the actual data and the margin test data, an error is declared. The Data Timing Margin[3:0] variable determines how much before and after the actual data sampling point the margin test data are latched. Therefore, the data timing margin variable determines how much setup and hold margin the interface needs for the data timing error IRQ to remain inactive (show error free operation). Therefore, the timing error IRQ is set whenever the setup and hold margins drop below the Data Timing Margin[3:0] value and does not necessarily indicate that the data latched into the device is incorrect.
When the device is placed into manual mode, the error checking logic is activated. If the IRQs are enabled, an interrupt is generated if a setup/hold violation is detected. One error check operation is performed per device configuration. Any change to the Data Timing Margin[3:0] or DATACLK Delay[3:0] values triggers a new error check operation.
Rev. B | Page 48 of 56
06452-403
ACTUAL SAMPLING INSTANT
AD9776A/AD9778A/AD9779A DEVICE SYNCHRONIZATION
System demands can impose two different requirements for synchronization. Some systems require multiple DACs to be synchronized to each other. This is the case when supporting transmit diversity or beam forming, where multiple antennas are used to transmit a correlated signal. In this case, the DAC outputs need to be phase aligned with each other, but there may not be a requirement for the DAC outputs to be aligned with a system level reference clock. In systems with a time division multiplexing transmit chain, one or more DACs may need to be synchronized with a system level reference clock. The options for synchronizing devices under these two conditions are described in the Synchronization Logic Overview section and the Synchronizing Devices to a System Clock section. multiple of 32 DACCLK periods. In any case, the maximum frequency of SYNC_I must be less than fDATACLK.
Table 30. Settings Required to Support Various SYNC_I Frequencies
SYNC_I Ratio[2:0] 000 001 010 011 100 101 110 111 SYNC_I Rising Edges Required for Synchronization Pulse 1 (default) 2 4 8 16 Invalid setting Invalid setting Invalid setting
SYNCHRONIZATION LOGIC OVERVIEW
Figure 88 shows the block diagram of the on-chip synchronization logic. The basic operation of the synchronization logic is to generate a single DACCLK-cycle-wide initialization pulse that sets the clock generation state machine logic to a known state. This initialization pulse loads the clock generation state machine with the Clock State[4:0] value as its next state. If the initialization pulse from the synchronization logic is generated properly, it is active for one DACCLK cycle, every 32 DACCLK cycles. Because the clock generation state machine has 32 states operating at the DACCLK rate, every initialization pulse received after the first pulse loads the state in which the state machine is already in, maintaining proper clocking operation of the device.
PLL BYPASS INTERNAL PLL DACCLK CLOCK GENERATION STATE MACHINE BIT 0 (1x INTERPOLATION) BIT 1 (2x) BIT 2 (4x) BIT 3 (8x) BIT 4 (8x WITH ZERO STUFFING) REFCLK
As an example, if a SYNC_I signal with a frequency of fDACCLK/4 is used, then both 011 and 100 are valid settings for the SYNC_I Ratio[2:0] value. A setting of 011 results in one initialization pulse being generated every 32 DACCLK cycles, and a setting of 100 results in one initialization pulse being generated every 64 DACCLK cycles. Both cases result in proper device synchronization. The Clock State[4:0] value is the state to which the clock generation state machine resets upon initialization. By varying this value, the timing of the internal clocks with respect to the SYNC_I signal can be adjusted. Every increment of the Clock State[4:0] value advances the internal clocks by one DACCLK period.
Synchronization Timing Error Detection
MUX
LOAD DACCLK OFFSET VALUE (REG 0x07, BITS[4:0]), ONE DACCLK CYCLE/INCREMENT
SYNC_I
SYNC DELAY DELAY REGISTER (REG 0x0, BITS[7:4])
ERROR DETECT CIRCUITRY
SYNC IRQ
Figure 88. Synchronization Circuitry Block Diagram
Nominally, the SYNC_I input should have one rising edge every 32 clock cycles (or multiple of 32 clock cycles) to maintain proper synchronization. The pulse generation logic can be programmed to suppress outgoing pulses if the incoming SYNC_I frequency is greater than DACCLK/32. Extra pulses can be suppressed by the ratios listed in Table 30. The SYNC_I frequency can be lower than DACCLK/32 as long as output pulses are generated from the pulse generation circuit on a
Rev. B | Page 49 of 56
06452-094
fSYNC_1 < fDATA/2^N
PULSE GENERATION LOGIC
The synchronization logic has error detection circuitry similar to the input data timing. The SYNC_I Timing Margin[3:0] variable determines how much setup and hold margin the synchronization interface needs for the sync timing error IRQ bit to remain inactive (that is, to indicate error free operation). Therefore, the sync timing error IRQ bit is set whenever the setup and hold margins drop below the SYNC_I Timing Margin[3:0] value and, therefore, does not necessarily indicate that the SYNC_I input was latched incorrectly. When the sync timing error IRQ bit is set, corrective action can be taken to restore timing margin. One course of action is to temporarily reduce the timing margin until the sync timing error IRQ is cleared. Then, increase the SYNC_I delay by two increments and check whether the timing margin has increased or decreased. If it has increased, continue incrementing the value of SYNC_I delay until the margin is maximized. However, if incrementing the SYNC_I delay reduced the timing margin, then the delay should be reduced until the timing margin is optimized.
AD9776A/AD9778A/AD9779A
SYNCHRONIZING DEVICES TO A SYSTEM CLOCK
The AD9776A/AD9778A/AD9779A offer a pulse mode synchronization scheme (see Figure 89) to align the DAC outputs of multiple devices within a system to the same DACCLK edge. The internal clocks are synchronized by providing either a onetime pulse or a periodic signal to the SYNC_I inputs (SYNC_I+, SYNC_I-). The SYNC_I signal is sampled by the internal DACCLK sample rate clock. The SYNC_I input frequency has the following constraint: fSYNC_I fDATA When the internal clocks are synchronized, the data-sampling clocks between all devices are phase aligned. The data input timing relationships can be referenced to either REFCLK or DATACLK. For this synchronization scheme, all devices are slave devices, and the system clock generation/distribution chip serves as the master. It is vital that the SYNC_I signal be distributed between the DACs with low skew. Likewise, the REFCLK signals must be distributed with low skew. Any skew on these signals between the DACs must be accounted for in the timing budget. Figure 89 shows an example clock and synchronization input scheme. Figure 90 shows the timing of the SYNC_I input with respect to the REFCLK input. Note that although the timing is relative to the REFCLK signal, SYNC_I is sampled at the DACCLK rate. This means that the rising edge of the SYNC_I signal must occur after the hold time of the preceding DACCLK rising edge, not the preceding REFCLK rising edge.
INTERRUPT REQUEST OPERATION
The IRQ pin (Pin 71) acts as an alert in the event that the device has a timing error and should be queried (by reading Register 0x19) to determine the exact fault condition. The IRQ pin is an open-drain, active low output. The IRQ pin should be pulled high external to the device. This pin can be tied to the IRQ pins of other devices with open-drain outputs to wire-OR these pins together. There are two different error flags that can trigger an interrupt request: a data timing error flag or a sync timing error flag. By default, when either or both of these error flags are set, the IRQ pin is active low. Either or both of these error flags can be masked to prevent them from activating an interrupt on the IRQ pin. The error flags are latched and remain active until the interrupt register, Register 0x19, is either read from or the error flag bits are overwritten.
MATCHED LENGTH TRACES REFCLK OUT SYNC_I
SYSTEM CLOCK
LOW SKEW CLOCK DRIVER REFCLK OUT SYNC_I
PULSE GENERATOR
LOW SKEW CLOCK DRIVER
MATCHED LENGTH TRACES
Figure 89. Multichip Synchronization in Pulse Mode
SYNC_I
tH_SYNC
REFCLK
tS_SYNC
DACCLK
Figure 90. Timing Diagram of SYNC_I with Respect to REFCLK When Synchronizing Multiple Devices to Each Other
Rev. B | Page 50 of 56
06452-312
06452-311
AD9776A/AD9778A/AD9779A POWER DISSIPATION
Figure 91 to Figure 99 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC mode and dual DAC mode. In addition to this, the power dissipation/current of the 3.3 V analog supply (mode and speed independent) in single DAC mode is 102 mW/31 mA. In dual DAC mode, this is 182 mW/55 mA. When the PLL is enabled, it adds 50 mA/90 mW to the 1.8 V clock supply.
0.7
8x INTERPOLATION
0.075
0.6 0.5
POWER (W)
8x INTERPOLATION, ZERO STUFFING
4x INTERPOLATION 4x INTERPOLATION, ZERO STUFFING
0.050 0.4 0.3 0.2
1x INTERPOLATION 2x INTERPOLATION, ZERO STUFFING 2x INTERPOLATION 1x INTERPOLATION, ZERO STUFFING
ALL INTERPOLATION MODES
0.1 0 0
06452-076
fDATA (MSPS)
fDATA (MSPS)
Figure 91. Total Power Dissipation, I Data Only, Real Mode
0.4
Figure 94. Power Dissipation, Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation Modes and Zero Stuffing
1.0 0.9
8x INTERPOLATION, ZERO STUFFING 8x INTERPOLATION, ALL MODULATION MODES 4x INTERPOLATION, ALL MODULATION MODES
8x INTERPOLATION 0.3
4x INTERPOLATION
0.8 0.7
POWER (W)
0.2
2x INTERPOLATION
POWER (W)
0.6 0.5 0.4 0.3
2x INTERPOLATION, ALL MODULATION MODES
0.1 1x INTERPOLATION
0.2 0.1
4x INTERPOLATION, ZERO STUFFING
2x INTERPOLATION, ZERO STUFFING 1x INTERPOLATION, ZERO STUFFING 1x INTERPOLATION
0
06452-078
fDATA (MSPS)
fDATA (MSPS)
Figure 92. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode, Does Not Include Zero Stuffing
0.08
0.8 0.7
Figure 95. Total Power Dissipation, Dual DAC Mode
8x INTERPOLATION, fDAC /8, fDAC /4, fDAC /2, NO MODULATION 4x INTERPOLATION
0.06
0.6
8x INTERPOLATION
4x INTERPOLATION
POWER (W)
POWER (W)
0.5 0.4 0.3 0.2
0.04 2x INTERPOLATION
2x INTERPOLATION
0.02 1x INTERPOLATION
0.1 0
06452-079
1x INTERPOLATION, NO MODULATION
0
fDATA (MSPS)
fDATA (MSPS)
Figure 93. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode, Includes Modulation Modes, Does Not Include Zero Stuffing
Figure 96. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC Mode, Does Not Include Zero Stuffing
Rev. B | Page 51 of 56
06452-081
0
25
50
75
100
125
150
175
200
225
250
0
25
50
75
100
125
150
175
200
225
250
06452-077
0
25
50
75
100
125
150
175
200
225
250
0
0
25
50
75
100 125 150 175 200 225 250 275 300
06452-080
0
POWER (W)
0.025
25
50
75
100
125
150
175
200
225
250
0
25
50
75
100
125
150
175
200
225
250
AD9776A/AD9778A/AD9779A
0.125 8x INTERPOLATION, fDAC /8, fDAC /4, fDAC /2, NO MODULATION 0.100
POWER-DOWN AND SLEEP MODES
4x INTERPOLATION
POWER (W)
0.075 2x INTERPOLATION 0.050
0.025 1x INTERPOLATION, NO MODULATION
06452-082
0
0
25
50
75
100
125
150
175
200
225
250
fDATA (MSPS)
Figure 97. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC Mode, Does Not Include Zero Stuffing
0.075
The AD9776A/AD9778A/AD9779A have a variety of power-down modes; thus, the digital engine, main TxDACs, or auxiliary DACs can be powered down individually or together. Via the 3-wire interface port, the main TxDACs can be placed in sleep or powerdown mode. In sleep mode, the TxDAC output is turned off, thus reducing power dissipation. The reference remains powered on, however, so that recovery from sleep mode is very fast. With the power-down mode bit set (Register 0x00, Bit 4), all analog and digital circuitry, including the reference, is powered down. The 3-wire interface port remains active in this mode. This mode offers more substantial power savings than sleep mode, but the turn-on time is much longer. The auxiliary DACs also have the capability to be programmed into sleep mode via the 3-wire interface port. The auto power-down enable bit (Register 0x00, Bit 3) controls the power-down function for the digital section of the devices. The auto power-down function works in conjunction with the TXENABLE pin (Pin 39); see Table 31 for details.
Table 31.
0.050
POWER (W)
ALL INTERPOLATION MODES
TXENABLE (Pin 39) 0
0.025
0
1
fDATA (MSPS)
06452-083
Description If auto power-down enable bit = 0, flush data path with 0s. If auto power-down enable bit = 1, flush data for multiple REFCLK cycles; then, automatically place the digital engine in power-down state. DACs, reference, and 3-wire interface port are not affected. Normal operation.
0
25
50
75
100
125
150
175
200
225
250
Figure 98. Power Dissipation, Digital 3.3 V Supply, I and Q Data, Dual DAC Mode
0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0
POWER (W)
fDAC (MSPS)
Figure 99. DVDD18 Power Dissipation of Inverse Sinc Filter
Rev. B | Page 52 of 56
06452-084
0
200
400
600
800
1000
1200
AD9776A/AD9778A/AD9779A EVALUATION BOARD OVERVIEW
EVALUATION BOARD OPERATION
The AD9776A/AD9778A/AD9779A evaluation board is provided to help users quickly become familiar with the operation of the device and to evaluate the device performance. To operate the evaluation board, the user needs a PC, a 5 V power supply, a clock source, and a digital data source. The user also needs a spectrum analyzer or an oscilloscope to observe the DAC output. The typical evaluation setup is shown in Figure 100. A sine or square wave clock can be used to source the DAC sample clock. The spectral purity of the clock directly affects the device performance. A low noise, low jitter clock source is required. All necessary connections to the evaluation board are shown in more detail in Figure 101.
CLOCK GENERATOR
ADAPTER CABLES
CLKIN
SPI PORT SPECTRUM ANALYZER
DIGITAL PATTERN GENERATOR CLOCK IN DATACLK OUT
AD9776A/ AD9778A/ AD9779A
EVALUATION BOARD
1.8V POWER SUPPLY 3.3V POWER SUPPLY
06452-097 06452-095
Figure 100. Typical Test Setup
DVDD18
DVDD33
CVDD18
AVDD33
J2 5V SUPPLY
P4 DIGITAL INPUT CONNECTOR
J1 CLOCK IN
JP4 JP15 JP8 JP14 JP3 JP16 JP2 JP17
MODULATOR OUTPUT S5 OUTPUT 1 ADL537x +5V GND
AD9779A
S7 DCLKOUT
S6 OUTPUT 2 LOCAL OSC INPUT ANALOG DEVICES AD9776A/ AD9778A/ AD9779A
SPI PORT
Figure 101. AD9776A/AD9778A/AD9779A Evaluation Board Showing All Connections
Rev. B | Page 53 of 56
AD9776A/AD9778A/AD9779A
The evaluation board comes with software that allows the user to program the on-chip configuration registers. Via the 3-wire interface port, the devices can be programmed into any of its various operating modes. The default software window is shown in Figure 102.
1. SET INTERPOLATION RATE 2. SET INTERPOLATION FILTER MODE 3. SET INPUT DATA FORMAT 4. SET DATACLK POLARITY TO MATCH INPUT TIMING
The evaluation board also comes populated with the ADL537x modulator to allow for the evaluation of an RF subsystem. Complete details on the evaluation board and the 3-wire interface software can be downloaded from the Analog Devices website.
Figure 102. 3-Wire Interface Port Software Window
Rev. B | Page 54 of 56
06452-099
AD9776A/AD9778A/AD9779A OUTLINE DIMENSIONS
0.75 0.60 0.45 SEATING PLANE 1.20 MAX
100 1 PIN 1
16.00 BSC SQ 14.00 BSC SQ
76 75 76 75 100 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE HEAT SINK 25 26 51 50 51 50 26 25
0.20 0.09 7 3.5 0
1.05 1.00 0.95
6.50 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.50 BSC
0.27 0.22 0.17
0.15 0.05
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HDT
Figure 103. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9776ABSVZ 1 AD9776ABSVZRL1 AD9778ABSVZ1 AD9778ABSVZRL1 AD9779ABSVZ1 AD9779ABSVZRL1 AD9776A-EBZ1 AD9778A-EBZ1 AD9779A-EBZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Evaluation Board Evaluation Board Evaluation Board
Package Option SV-100-1 SV-100-1 SV-100-1 SV-100-1 SV-100-1 SV-100-1
Z = RoHS Compliant Part.
Rev. B | Page 55 of 56
072408-A
AD9776A/AD9778A/AD9779A NOTES
(c)2007-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06452-0-9/08(B)
Rev. B | Page 56 of 56

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